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git-svn-id: file:///srv/svn/repos/haiku/trunk/current@8416 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen
2004-07-18 16:35:36 +00:00
parent d826fa6fa7
commit f24cfa8680
2 changed files with 4 additions and 6 deletions
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src/add-ons/kernel/bus_managers/agp/README.html
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@@ -76,7 +76,7 @@ This option is disabled by default (preceded by a '#').<br>
<li><strong>block_sba:</strong> (set to 'false' by default)<br>
If set to 'true' this option blocks use of sideband adressing. Sideband adressing speeds up AGP transfers a bit because it's a seperate (low-speed) communications 'channel' that's used alongside the main transfer channel concurrently. So this enables 'full-duplex' communications, while disabling SBA forces the hardware to use 'half-duplex' communications.
<li><strong>block_fw:</strong> (set to 'false' by default)<br>
If set to 'true' this option blocks use of PCI fastwrites. PCI fastwrites work in the same speed AGP transfers work. This means PCI fastwrites are faster in AGP4x mode than they are in AGP2x mode (for instance). PCI fastwrites are used whenever the system initializes transfers to or from the graphicscard, while 'standard PCI' or AGP transfers are used if the graphicscard's acceleration engine initializes transfers to or from the system.<br>
If set to 'true' this option blocks use of PCI fastwrites. PCI fastwrites work in the same speed AGP transfers work. This means PCI fastwrites are faster in AGP4x mode than they are in AGP2x mode (for instance). PCI fastwrites are used whenever the system initializes transfers to the graphicscard, while 'standard PCI' or AGP transfers are used if the graphicscard's acceleration engine initializes transfers to or from the system.<br>
This means that PCI FW is the only AGP 'feature' that has an effect on the graphics speed on BeOS as it is currently. The use of AGP transfers require graphicsdriver support, and these type of transfers are 'officially' targeted specific for hardware accelerated 3D (which we do not yet have).<br>
<strong>Note:</strong><br>
PCI FW support was first introduced with the AGP2.0 specification: that is, devices that support upto and including AGP4X mode are candidates to have this feature.
@@ -84,6 +84,6 @@ PCI FW support was first introduced with the AGP2.0 specification: that is, devi
<hr>
<br>
<a href="mailto:[email protected]">Rudolf Cornelissen.</a>
<p>(Page last updated on July 17, 2004)</p>
<p>(Page last updated on July 18, 2004)</p>
</body>
</html>
src/add-ons/kernel/bus_managers/agp/agp.cpp
+2 -4
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@@ -347,11 +347,9 @@ void enable_agp (uint32 *command)
if (pd->di[count].agpi.class_base == PCI_bridge)
{
pcii = &(pd->di[count].pcii);
/* program bridge */
set_pci(pd->di[count].agp_adress + 8, 4, *command);
/* program bridge, making sure not-implemented bits are written as zeros */
set_pci(pd->di[count].agp_adress + 8, 4, (*command & ~(AGP_rate_rev | AGP_RQ)));
/* update our agp_cmd info with read back setting from register just programmed */
/* note:
* this 'sequence' resets the non-writable register bit AGP_rate_rev in our info */
pd->di[count].agpi.interface.agp_cmd = get_pci(pd->di[count].agp_adress + 8, 4);
}
}