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intel_extreme: Set FDI PLL RX lane count when enabling

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This commit is contained in:
Alexander von Gluck IV
2016-07-20 00:25:38 -05:00
parent 04039d6f30
commit f6c32ce310
3 changed files with 19 additions and 7 deletions
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headers/private/graphics/intel_extreme/intel_extreme.h
+4
View File
@@ -878,6 +878,10 @@ struct intel_free_graphics_memory {
#define FDI_TX_ENHANCE_FRAME_ENABLE (1 << 18) #define FDI_TX_ENHANCE_FRAME_ENABLE (1 << 18)
#define FDI_TX_PLL_ENABLED (1 << 14) #define FDI_TX_PLL_ENABLED (1 << 14)
#define FDI_DP_PORT_WIDTH_SHIFT 19
#define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT)
#define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
#define FDI_PLL_BIOS_0 0x46000 #define FDI_PLL_BIOS_0 0x46000
#define FDI_PLL_FB_CLOCK_MASK 0xff #define FDI_PLL_FB_CLOCK_MASK 0xff
#define FDI_PLL_BIOS_1 0x46004 #define FDI_PLL_BIOS_1 0x46004
src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp
+13 -5
View File
@@ -84,13 +84,14 @@ FDITransmitter::IsPLLEnabled()
void void
FDITransmitter::EnablePLL() FDITransmitter::EnablePLL(uint32 lanes)
{ {
CALLED(); CALLED();
uint32 targetRegister = fRegisterBase + PCH_FDI_TX_CONTROL; uint32 targetRegister = fRegisterBase + PCH_FDI_TX_CONTROL;
uint32 value = read32(targetRegister); uint32 value = read32(targetRegister);
if ((value & FDI_TX_PLL_ENABLED) != 0) { if ((value & FDI_TX_PLL_ENABLED) != 0) {
// already enabled, possibly IronLake where it always is // already enabled, possibly IronLake where it always is
TRACE("%s: Already enabled.\n", __func__);
return; return;
} }
@@ -169,13 +170,20 @@ FDIReceiver::IsPLLEnabled()
void void
FDIReceiver::EnablePLL() FDIReceiver::EnablePLL(uint32 lanes)
{ {
CALLED(); CALLED();
uint32 targetRegister = fRegisterBase + PCH_FDI_RX_CONTROL; uint32 targetRegister = fRegisterBase + PCH_FDI_RX_CONTROL;
uint32 value = read32(targetRegister); uint32 value = read32(targetRegister);
if ((value & FDI_RX_PLL_ENABLED) != 0) if ((value & FDI_RX_PLL_ENABLED) != 0) {
// already enabled, possibly IronLake where it always is
TRACE("%s: Already enabled.\n", __func__);
return; return;
}
value &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
value |= FDI_DP_PORT_WIDTH(lanes);
//value |= (read32(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
write32(targetRegister, value | FDI_RX_PLL_ENABLED); write32(targetRegister, value | FDI_RX_PLL_ENABLED);
read32(targetRegister); read32(targetRegister);
@@ -248,9 +256,9 @@ FDILink::Train(display_mode* target)
TRACE("%s: FDI Link Lanes: %" B_PRIu32 "\n", __func__, lanes); TRACE("%s: FDI Link Lanes: %" B_PRIu32 "\n", __func__, lanes);
// Enable FDI clocks // Enable FDI clocks
Receiver().EnablePLL(); Receiver().EnablePLL(lanes);
Receiver().SwitchClock(true); Receiver().SwitchClock(true);
Transmitter().EnablePLL(); Transmitter().EnablePLL(lanes);
status_t result = B_ERROR; status_t result = B_ERROR;
src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.h
+2 -2
View File
@@ -22,7 +22,7 @@ public:
void Disable(); void Disable();
bool IsPLLEnabled(); bool IsPLLEnabled();
void EnablePLL(); void EnablePLL(uint32 lanes);
void DisablePLL(); void DisablePLL();
uint32 Base() uint32 Base()
@@ -42,7 +42,7 @@ public:
void Disable(); void Disable();
bool IsPLLEnabled(); bool IsPLLEnabled();
void EnablePLL(); void EnablePLL(uint32 lanes);
void DisablePLL(); void DisablePLL();
void SwitchClock(bool toPCDClock); void SwitchClock(bool toPCDClock);