intel_extreme: disable pipe configuration

This code just sets nonsensical things in the pipe control register, so
disable it and add FIXMEs if someone wants to get it to work someday
(but it's not needed for modesetting an already up and running display).

Also remove some other places where we write to non-existing registers.

Fixes #15628 (for real, this time).
This commit is contained in:
Adrien Destugues
2020-01-25 19:48:48 +01:00
parent 1fa0a12d75
commit fadca4b173
2 changed files with 29 additions and 12 deletions
@@ -101,11 +101,19 @@ Pipe::IsEnabled()
void
Pipe::Configure(display_mode* mode)
{
#if 0
// FIXME the previous values are never masked out from the
// register, so we just OR things together and hope to fall on a working
// mode. Better do nothing at all for now.
uint32 pipeControl = read32(INTEL_DISPLAY_A_PIPE_CONTROL + fPipeOffset);
// TODO: Haswell+ dithering changes.
if (gInfo->shared_info->device_type.Generation() >= 4) {
pipeControl |= (INTEL_PIPE_DITHER_EN | INTEL_PIPE_DITHER_TYPE_SP);
// FIXME this makes no sense, if only because B_CMAP8, B_RGB24 and
// B_RGB32 have the same color precision (8bit per component).
// Also because the color mode is a property of the hardware
// (depends on which LVDS panel is used, typically), not the video mode.
switch (mode->space) {
case B_CMAP8:
case B_RGB15_LITTLE:
@@ -129,6 +137,7 @@ Pipe::Configure(display_mode* mode)
write32(INTEL_DISPLAY_A_PIPE_CONTROL + fPipeOffset, pipeControl);
read32(INTEL_DISPLAY_A_PIPE_CONTROL + fPipeOffset);
#endif
}
@@ -209,25 +218,36 @@ Pipe::ConfigureTimings(display_mode* target, bool hardware)
| ((uint32)target->timing.v_sync_start - 1));
}
if (gInfo->shared_info->device_type.Generation() != 6) {
// FIXME check on which generations this register exists
// (it appears it would be available only for cursor planes, not
// display planes)
// Since we set the plane to be the same size as the display, we can
// just show it starting at top-left.
write32(INTEL_DISPLAY_A_POS + fPipeOffset, 0);
}
// The only thing that really matters: set the image size and let the
// panel fitter or the transcoder worry about the rest
write32(INTEL_DISPLAY_A_PIPE_SIZE + fPipeOffset,
((uint32)(target->timing.h_display - 1) << 16)
| ((uint32)target->timing.v_display - 1));
((uint32)(target->virtual_width - 1) << 16)
| ((uint32)target->virtual_height - 1));
// Set the plane size as well while we're at it (this is independant, we
// could have a larger plane and scroll through it).
if (gInfo->shared_info->device_type.Generation() > 4) {
if (gInfo->shared_info->device_type.Generation() == 5
|| gInfo->shared_info->device_type.Generation() > 6) {
// FIXME check which generations actually need this.
// This is "reserved" on G45 and below.
// This register does not exist on generation 6.
write32(INTEL_DISPLAY_A_IMAGE_SIZE + fPipeOffset,
((uint32)(target->virtual_width - 1) << 16)
| ((uint32)target->virtual_height - 1));
}
// Since we set the plane to be the same size as the display, we can just
// show it starting at top-left.
write32(INTEL_DISPLAY_A_POS + fPipeOffset, 0);
if (fHasTranscoder)
if (fHasTranscoder && hardware) {
_ConfigureTranscoder(target);
}
}
@@ -285,9 +285,6 @@ intel_set_display_mode(display_mode* mode)
display_mode target = *mode;
// TODO: it may be acceptable to continue when using panel fitting or
// centering, since the data from propose_display_mode will not actually be
// used as is in this case.
if (sanitize_display_mode(target)) {
TRACE("Video mode was adjusted by sanitize_display_mode\n");
TRACE("Initial mode: Hd %d Hs %d He %d Ht %d Vd %d Vs %d Ve %d Vt %d\n",
@@ -326,7 +323,7 @@ intel_set_display_mode(display_mode* mode)
if (intel_allocate_memory(bytesPerRow * target.virtual_height, 0,
base) < B_OK) {
// oh, how did that happen? Unfortunately, there is no really good way
// back
// back. Try to restore a framebuffer for the previous mode, at least.
if (intel_allocate_memory(gInfo->current_mode.virtual_height
* sharedInfo.bytes_per_row, 0, base) == B_OK) {
sharedInfo.frame_buffer = base;