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ice1712 - Refactoring

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- Change C source code to C++
- Fix build warning for x86 and x86_64 version
- Re-organize source code
- Change copyright

Signed-off-by: Jerome Duval <[email protected]>
This commit is contained in:
Jerome Leveque
2015-03-03 22:09:20 +01:00
committed by Jérôme Duval
parent ed1f97b0b4
commit ffb788fe58
14 changed files with 1387 additions and 1424 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/add-ons/kernel/drivers/audio/ice1712/Jamfile
+5 -5
View File
@@ -5,10 +5,10 @@ SetSubDirSupportedPlatformsBeOSCompatible ;
UsePrivateHeaders media ;
KernelAddon ice1712 :
ice1712.c
io.c
midi.c
multi.c
util.c
ice1712.cpp
io.cpp
midi.cpp
multi.cpp
util.cpp
;
src/add-ons/kernel/drivers/audio/ice1712/debug.h
+12 -19
View File
@@ -1,36 +1,29 @@
/*
* ice1712 BeOS/Haiku Driver for VIA - VT1712 Multi Channel Audio Controller
* Copyright 2004-2015 Haiku, Inc. All rights reserved.
* Distributed under the terms of the MIT License.
*
* Copyright (c) 2002, Jerome Duval ([email protected])
* Copyright (c) 2003, Marcus Overhagen ([email protected])
* Copyright (c) 2007, Jerome Leveque ([email protected])
*
* All rights reserved
* Distributed under the terms of the MIT license.
* Authors:
* Jérôme Duval, [email protected]
* Marcus Overhagen, [email protected]
* Jérôme Lévêque, [email protected]
*/
#ifndef _DEBUG_ICE1712_H_
#define _DEBUG_ICE1712_H_
#ifdef TRACE
# undef TRACE
#endif
//#define ICE1712_VERBOSE
#ifdef ICE1712_VERBOSE
# define TRACE(a...) dprintf("\33[34mice1712:\33[0m " a)
# define ITRACE(a...) dprintf("ice1712: " a)
#else
# define TRACE(a...) ;
# define ITRACE(a...) (void)0
#endif
//#define ICE1712_VERY_VERBOSE
#ifdef ICE1712_VERY_VERBOSE
# define TRACE_VV(a...) dprintf("\33[34mice1712:\33[0m " a)
# define ITRACE_VV(a...) ITRACE(a)
#else
# define TRACE_VV(a...) ;
# define ITRACE_VV(a...) (void)0
#endif
#define ASSERT(a) if (a) {} else TRACE("ASSERT failed! file = %s, line = %d\n",\
__FILE__,__LINE__)
#endif // _DEBUG_ICE1712_H_
src/add-ons/kernel/drivers/audio/ice1712/ice1712.c → src/add-ons/kernel/drivers/audio/ice1712/ice1712.cpp
+289 -311
View File
@@ -1,12 +1,11 @@
/*
* ice1712 BeOS/Haiku Driver for VIA - VT1712 Multi Channel Audio Controller
* Copyright 2004-2015 Haiku, Inc. All rights reserved.
* Distributed under the terms of the MIT License.
*
* Copyright (c) 2002, Jerome Duval (jerome.duval@free.fr)
* Copyright (c) 2003, Marcus Overhagen (marcus@overhagen.de)
* Copyright (c) 2007, Jerome Leveque (leveque.jerome@neuf.fr)
*
* All rights reserved
* Distributed under the terms of the MIT license.
* Authors:
* Jérôme Duval, jerome.duval@free.fr
* Marcus Overhagen, marcus@overhagen.de
* Jérôme Lévêque, leveque.jerome@gmail.com
*/
@@ -26,43 +25,49 @@
#include <stdlib.h>
#include <string.h>
static status_t ice1712Settings_load(ice1712 *card);
status_t ice1712Settings_apply(ice1712 *card);
static int32 ice1712HW_interrupt(void *arg);
static status_t ice1712HW_setup(ice1712 *ice);
static void ice1712HW_shutdown(ice1712 *ice);
status_t init_hardware(void);
status_t init_driver(void);
void uninit_driver(void);
const char **publish_devices(void);
device_hooks *find_device(const char *);
status_t load_settings(ice1712 *card);
int32 ice_1712_int(void *arg);
extern device_hooks ice1712Midi_hooks;
extern device_hooks ice1712Audio_hooks;
void ice1712Midi_interrupt(int32 op, void *data);
pci_module_info *pci;
generic_mpu401_module *mpu401;
int32 num_cards = 0;
ice1712 cards[NUM_CARDS];
int32 num_names = 0;
char *names[NUM_CARDS*20+1];
int32 api_version = B_CUR_DRIVER_API_VERSION;
//3 interfaces (2 midi + 1 audio) can be defined for each card
static char *names[NUM_CARDS*3+1];
static int32 num_names = 0;
#define HMULTI_AUDIO_DEV_PATH "audio/hmulti/ice1712"
//Haiku Driver API
//----------------
status_t
int32 api_version = B_CUR_DRIVER_API_VERSION;
extern "C" status_t
init_hardware(void)
{
int ix = 0;
pci_info info;
memset(cards, 0, sizeof(ice1712) * NUM_CARDS);
TRACE("@@init_hardware()\n");
ITRACE("@@ init_hardware()\n");
if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci))
return ENOSYS;
while ((*pci->get_nth_pci_info)(ix, &info) == B_OK) {
if ((info.vendor_id == ICE1712_VENDOR_ID) &&
(info.device_id == ICE1712_DEVICE_ID)) {
TRACE("Found at least 1 card\n");
if ((info.vendor_id == ICE1712_VENDOR_ID)
&& (info.device_id == ICE1712_DEVICE_ID)) {
ITRACE("Found at least 1 card\n");
put_module(B_PCI_MODULE_NAME);
return B_OK;
}
@@ -73,10 +78,133 @@ init_hardware(void)
}
int32
ice_1712_int(void *arg)
extern "C" status_t
init_driver(void)
{
ice1712 *ice = arg;
int i = 0;
status_t err;
num_cards = 0;
ITRACE("@@ init_driver()\n");
if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci))
return ENOSYS;
if (get_module(B_MPU_401_MODULE_NAME, (module_info **) &mpu401)) {
put_module(B_PCI_MODULE_NAME);
return ENOSYS;
}
while ((*pci->get_nth_pci_info)(i, &cards[num_cards].info) == B_OK) {
//TODO check other Vendor_ID and DEVICE_ID
if ((cards[num_cards].info.vendor_id == ICE1712_VENDOR_ID)
&& (cards[num_cards].info.device_id == ICE1712_DEVICE_ID)) {
if (num_cards == NUM_CARDS) {
ITRACE("Too many ice1712 cards installed!\n");
break;
}
if ((err = (*pci->reserve_device)(cards[num_cards].info.bus,
cards[num_cards].info.device,
cards[num_cards].info.function,
DRIVER_NAME, &cards[num_cards])) < B_OK) {
ITRACE_VV("%s: failed to reserve_device(%d, %d, %d,): %s\n",
DRIVER_NAME, cards[num_cards].info.bus,
cards[num_cards].info.device,
cards[num_cards].info.function, strerror(err));
continue;
}
ice1712Settings_load(&cards[num_cards]);
if (ice1712HW_setup(&cards[num_cards]) != B_OK) {
//Vendor_ID and Device_ID has been modified
ITRACE("Setup of ice1712 %" B_PRIu32 " failed\n", num_cards + 1);
(*pci->unreserve_device)(cards[num_cards].info.bus,
cards[num_cards].info.device,
cards[num_cards].info.function,
DRIVER_NAME, &cards[num_cards]);
} else {
num_cards++;
}
}
i++;
}
ITRACE("Succesfully initialised card : %" B_PRIu32 "\n", num_cards);
if (num_cards == 0) {
put_module(B_PCI_MODULE_NAME);
put_module(B_MPU_401_MODULE_NAME);
return ENODEV;
}
return B_OK;
}
extern "C" void
uninit_driver(void)
{
int ix, cnt = num_cards;
ITRACE("@@ uninit_driver()\n");
num_cards = 0;
for (ix = 0; ix < cnt; ix++) {
ice1712HW_shutdown(&cards[ix]);
(*pci->unreserve_device)(cards[ix].info.bus,
cards[ix].info.device, cards[ix].info.function,
DRIVER_NAME, &cards[ix]);
}
memset(&cards, 0, sizeof(cards));
put_module(B_MPU_401_MODULE_NAME);
put_module(B_PCI_MODULE_NAME);
}
extern "C" const char **
publish_devices(void)
{
int ix = 0;
ITRACE("@@ publish_devices()\n");
for (ix = 0; names[ix]; ix++) {
ITRACE("publish %s\n", names[ix]);
}
return (const char **)names;
}
extern "C" device_hooks *
find_device(const char * name)
{
int ix, midi;
ITRACE("@@ find_device()\n");
for (ix = 0; ix < num_cards; ix++) {
for (midi = 0; midi < MAX_MIDI_INTERFACE; midi++) {
if (!strcmp(cards[ix].midiItf[midi].name, name)) {
return &ice1712Midi_hooks;
}
}
if (!strcmp(cards[ix].name, name)) {
return &ice1712Audio_hooks;
}
}
ITRACE("!!! failed !!!\n");
return NULL;
}
//ICE1712 driver - Hardware
//-------------------------
int32
ice1712HW_interrupt(void *arg)
{
ice1712 *ice = (ice1712*)arg;
uint8 reg8 = 0;
uint16 reg16 = 0;
uint32 status = B_UNHANDLED_INTERRUPT;
@@ -98,7 +226,7 @@ ice_1712_int(void *arg)
if (reg8 != 0) {
bool ret;
if (reg8 & CCS_INTERRUPT_MIDI_1) {
ret = (*mpu401->interrupt_hook)(ice->midi_interf[0].mpu401device);
ret = (*mpu401->interrupt_hook)(ice->midiItf[0].mpu401device);
if (ret) {
//Do not ack, cause more datas are available
reg8 &= ~CCS_INTERRUPT_MIDI_1;
@@ -106,7 +234,7 @@ ice_1712_int(void *arg)
}
if (reg8 & CCS_INTERRUPT_MIDI_2) {
ret = (*mpu401->interrupt_hook)(ice->midi_interf[1].mpu401device);
ret = (*mpu401->interrupt_hook)(ice->midiItf[1].mpu401device);
if (ret) {
//Do not ack, cause more datas are available
reg8 &= ~CCS_INTERRUPT_MIDI_2;
@@ -131,18 +259,18 @@ ice_1712_int(void *arg)
}
static status_t
ice1712_setup(ice1712 *ice)
status_t
ice1712HW_setup(ice1712 *ice)
{
int i;
uint8 reg8 = 0;
uint16 mute;
ice->irq = ice->info.u.h0.interrupt_line;
ice->Controller = ice->info.u.h0.base_registers[0];
ice->DDMA = ice->info.u.h0.base_registers[1];
ice->DMA_Path = ice->info.u.h0.base_registers[2];
ice->Multi_Track = ice->info.u.h0.base_registers[3];
ice->irq = ice->info.u.h0.interrupt_line;
ice->Controller = ice->info.u.h0.base_registers[0];
ice->DDMA = ice->info.u.h0.base_registers[1];
ice->DMA_Path = ice->info.u.h0.base_registers[2];
ice->Multi_Track = ice->info.u.h0.base_registers[3];
// Soft Reset
write_ccs_uint8(ice, CCS_CONTROL_STATUS, 0x81);
@@ -152,11 +280,6 @@ ice1712_setup(ice1712 *ice)
read_eeprom(ice, ice->eeprom_data);
/* TRACE("EEprom -> ");
for (i = 0; i < 32; i++)
TRACE("%x, ", eeprom_data[i]);
TRACE("<- EEprom\n");*/
write_ccs_uint8(ice, CCS_SERR_SHADOW, 0x01);
//Write all configurations register from EEProm
@@ -164,8 +287,9 @@ ice1712_setup(ice1712 *ice)
| ice->eeprom_data[E2PROM_MAP_SUBVENDOR_LOW];
ice->info.vendor_id = ice->eeprom_data[E2PROM_MAP_SUBDEVICE_HIGH] << 8
| ice->eeprom_data[E2PROM_MAP_SUBDEVICE_LOW];
ice->product = ice->info.vendor_id << 16 | ice->info.device_id;
TRACE("Product ID : 0x%x\n", ice->product);
ice->config.product = (ice1712Product)(ice->info.vendor_id << 16
| ice->info.device_id);
ITRACE("Product ID : 0x%x\n", ice->config.product);
write_cci_uint8(ice, CCI_GPIO_WRITE_MASK,
ice->eeprom_data[E2PROM_MAP_GPIOMASK]);
@@ -174,14 +298,13 @@ ice1712_setup(ice1712 *ice)
write_cci_uint8(ice, CCI_GPIO_DIRECTION_CONTROL,
ice->eeprom_data[E2PROM_MAP_GPIODIR]);
TRACE("CCI_GPIO_WRITE_MASK : 0x%x\n",
ITRACE("CCI_GPIO_WRITE_MASK : 0x%x\n",
ice->eeprom_data[E2PROM_MAP_GPIOMASK]);
TRACE("CCI_GPIO_DATA : 0x%x\n",
ITRACE("CCI_GPIO_DATA : 0x%x\n",
ice->eeprom_data[E2PROM_MAP_GPIOSTATE]);
TRACE("CCI_GPIO_DIRECTION_CONTROL : 0x%x\n",
ITRACE("CCI_GPIO_DIRECTION_CONTROL : 0x%x\n",
ice->eeprom_data[E2PROM_MAP_GPIODIR]);
//Write Configuration in the PCI configuration Register
(pci->write_pci_config)(ice->info.bus, ice->info.device,
ice->info.function, 0x60, 1, ice->eeprom_data[E2PROM_MAP_CONFIG]);
@@ -192,7 +315,7 @@ ice1712_setup(ice1712 *ice)
(pci->write_pci_config)(ice->info.bus, ice->info.device,
ice->info.function, 0x63, 1, ice->eeprom_data[E2PROM_MAP_SPDIF]);
TRACE("E2PROM_MAP_CONFIG : 0x%x\n", ice->eeprom_data[E2PROM_MAP_CONFIG]);
ITRACE("E2PROM_MAP_CONFIG : 0x%x\n", ice->eeprom_data[E2PROM_MAP_CONFIG]);
reg8 = ice->eeprom_data[E2PROM_MAP_CONFIG];
//Bits signification for E2PROM_MAP_CONFIG Byte
//
@@ -210,52 +333,50 @@ ice1712_setup(ice1712 *ice)
reg8 >>= 2;
if ((reg8 & 0x01) != 0) {//Consumer AC'97 Exist
TRACE("Consumer AC'97 does exist\n");
ITRACE("Consumer AC'97 does exist\n");
//For now do nothing
/* write_ccs_uint8(ice, CCS_CONS_AC97_COMMAND_STATUS, 0x40);
snooze(10000);
write_ccs_uint8(ice, CCS_CONS_AC97_COMMAND_STATUS, 0x00);
snooze(20000);
*/ } else {
TRACE("Consumer AC'97 does NOT exist\n");
ITRACE("Consumer AC'97 does NOT exist\n");
}
reg8 >>= 1;
ice->config.nb_MPU401 = (reg8 & 0x1) + 1;
if (ice->config.nb_MPU401 > 0) {
sprintf(ice->midi_interf[0].name, "midi/ice1712/%ld/1",
ice - cards + 1);
sprintf(ice->midiItf[0].name, "midi/ice1712/%ld/1", ice - cards + 1);
(*mpu401->create_device)(ice->Controller + CCS_MIDI_1_DATA,
&ice->midi_interf[0].mpu401device,
&ice->midiItf[0].mpu401device,
0x14121712,
ice_1712_midi_interrupt_op,
&ice->midi_interf[0]);
ice1712Midi_interrupt,
&ice->midiItf[0]);
names[num_names++] = ice->midi_interf[0].name;
ice->midi_interf[0].card = ice;
ice->midi_interf[0].int_mask = CCS_INTERRUPT_MIDI_1;
names[num_names++] = ice->midiItf[0].name;
ice->midiItf[0].card = ice;
ice->midiItf[0].int_mask = CCS_INTERRUPT_MIDI_1;
}
if (ice->config.nb_MPU401 > 1) {
sprintf(ice->midi_interf[1].name, "midi/ice1712/%ld/2",
ice - cards + 1);
sprintf(ice->midiItf[1].name, "midi/ice1712/%ld/2", ice - cards + 1);
(*mpu401->create_device)(ice->Controller + CCS_MIDI_2_DATA,
&ice->midi_interf[1].mpu401device,
&ice->midiItf[1].mpu401device,
0x14121712,
ice_1712_midi_interrupt_op,
&ice->midi_interf[1]);
ice1712Midi_interrupt,
&ice->midiItf[1]);
names[num_names++] = ice->midi_interf[1].name;
ice->midi_interf[1].card = ice;
ice->midi_interf[1].int_mask = CCS_INTERRUPT_MIDI_2;
names[num_names++] = ice->midiItf[1].name;
ice->midiItf[1].card = ice;
ice->midiItf[1].int_mask = CCS_INTERRUPT_MIDI_2;
}
TRACE("E2PROM_MAP_SPDIF : 0x%x\n", ice->eeprom_data[E2PROM_MAP_SPDIF]);
ITRACE("E2PROM_MAP_SPDIF : 0x%x\n", ice->eeprom_data[E2PROM_MAP_SPDIF]);
ice->config.spdif = ice->eeprom_data[E2PROM_MAP_SPDIF];
switch (ice->product) {
switch (ice->config.product) {
case ICE1712_SUBDEVICE_DELTA66 :
case ICE1712_SUBDEVICE_DELTA44 :
ice->CommLines.clock = DELTA66_CLK;
@@ -299,32 +420,26 @@ ice1712_setup(ice1712 *ice)
return ice->buffer_ready_sem;
}
// TRACE("installing interrupt : %0x\n", ice->irq);
install_io_interrupt_handler(ice->irq, ice_1712_int, ice, 0);
install_io_interrupt_handler(ice->irq, ice1712HW_interrupt, ice, 0);
ice->mem_id_pb = alloc_mem(&ice->phys_addr_pb, &ice->log_addr_pb,
PLAYBACK_BUFFER_TOTAL_SIZE,
"playback buffer");
ice->mem_id_pb = alloc_mem(&ice->phys_pb, &ice->log_addr_pb,
PLAYBACK_BUFFER_TOTAL_SIZE, "playback buffer");
if (ice->mem_id_pb < B_OK) {
remove_io_interrupt_handler(ice->irq, ice_1712_int, ice);
remove_io_interrupt_handler(ice->irq, ice1712HW_interrupt, ice);
delete_sem(ice->buffer_ready_sem);
return ice->mem_id_pb;
}
ice->mem_id_rec = alloc_mem(&ice->phys_addr_rec, &ice->log_addr_rec,
RECORD_BUFFER_TOTAL_SIZE,
"record buffer");
ice->mem_id_rec = alloc_mem(&ice->phys_rec, &ice->log_addr_rec,
RECORD_BUFFER_TOTAL_SIZE, "record buffer");
if (ice->mem_id_rec < B_OK) {
remove_io_interrupt_handler(ice->irq, ice_1712_int, ice);
remove_io_interrupt_handler(ice->irq, ice1712HW_interrupt, ice);
delete_sem(ice->buffer_ready_sem);
delete_area(ice->mem_id_pb);
return(ice->mem_id_rec);
}
memset(ice->log_addr_pb, 0, PLAYBACK_BUFFER_TOTAL_SIZE);
memset(ice->log_addr_rec, 0, RECORD_BUFFER_TOTAL_SIZE);
ice->sampling_rate = 0x08;
ice->config.samplingRate = 0x08;
ice->buffer = 0;
ice->frames_count = 0;
ice->buffer_size = ice->settings.bufferSize;
@@ -346,17 +461,9 @@ ice1712_setup(ice1712 *ice)
write_mt_uint16(ice, MT_VOLUME_CONTROL_RATE, 0x01);
//All Analog outputs from DMA
write_mt_uint16(ice, MT_ROUTING_CONTROL_PSDOUT, 0x0000);
write_mt_uint16(ice, MT_ROUTING_CONTROL_PSDOUT, 0x0000);
//All Digital output from DMA
write_mt_uint16(ice, MT_ROUTING_CONTROL_SPDOUT, 0x0000);
//Just to route all input to all output
// write_mt_uint16(ice, MT_ROUTING_CONTROL_PSDOUT, 0xAAAA);
// write_mt_uint32(ice, MT_CAPTURED_DATA, 0x76543210);
//Just to route SPDIF Input to DAC 0
// write_mt_uint16(ice, MT_ROUTING_CONTROL_PSDOUT, 0xAAAF);
// write_mt_uint32(ice, MT_CAPTURED_DATA, 0x76543280);
write_mt_uint16(ice, MT_ROUTING_CONTROL_SPDOUT, 0x0000);
//Mute all input
mute = (ICE1712_MUTE_VALUE << 0) | (ICE1712_MUTE_VALUE << 8);
@@ -369,90 +476,27 @@ ice1712_setup(ice1712 *ice)
write_ccs_uint8(ice, CCS_CONTROL_STATUS, 0x41);
reg8 = read_ccs_uint8(ice, CCS_INTERRUPT_MASK);
TRACE("-----CCS----- = %x\n", reg8);
ITRACE("-----CCS----- = %x\n", reg8);
write_ccs_uint8(ice, CCS_INTERRUPT_MASK, 0xEF);
/* reg16 = read_ds_uint16(ice, DS_DMA_INT_MASK);
TRACE("-----DS_DMA----- = %x\n", reg16);
ITRACE("-----DS_DMA----- = %x\n", reg16);
write_ds_uint16(ice, DS_DMA_INT_MASK, 0x0000);
*/
reg8 = read_mt_uint8(ice, MT_DMA_INT_MASK_STATUS);
TRACE("-----MT_DMA----- = %x\n", reg8);
ITRACE("-----MT_DMA----- = %x\n", reg8);
write_mt_uint8(ice, MT_DMA_INT_MASK_STATUS, 0x00);
return B_OK;
};
status_t
init_driver(void)
{
int i = 0;
status_t err;
num_cards = 0;
TRACE("@@init_driver()\n");
if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci))
return ENOSYS;
if (get_module(B_MPU_401_MODULE_NAME, (module_info **) &mpu401)) {
put_module(B_PCI_MODULE_NAME);
return ENOSYS;
}
while ((*pci->get_nth_pci_info)(i, &cards[num_cards].info) == B_OK) {
//TODO check other Vendor_ID and DEVICE_ID
if ((cards[num_cards].info.vendor_id == ICE1712_VENDOR_ID)
&& (cards[num_cards].info.device_id == ICE1712_DEVICE_ID)) {
if (num_cards == NUM_CARDS) {
TRACE("Too many ice1712 cards installed!\n");
break;
}
if ((err = (*pci->reserve_device)(cards[num_cards].info.bus,
cards[num_cards].info.device, cards[num_cards].info.function,
DRIVER_NAME, &cards[num_cards])) < B_OK) {
dprintf("%s: failed to reserve_device(%d, %d, %d,): %s\n",
DRIVER_NAME, cards[num_cards].info.bus,
cards[num_cards].info.device,
cards[num_cards].info.function, strerror(err));
continue;
}
load_settings(&cards[num_cards]);
if (ice1712_setup(&cards[num_cards]) != B_OK) {
//Vendor_ID and Device_ID has been modified
TRACE("Setup of ice1712 %d failed\n", (int)(num_cards + 1));
(*pci->unreserve_device)(cards[num_cards].info.bus,
cards[num_cards].info.device,
cards[num_cards].info.function,
DRIVER_NAME, &cards[num_cards]);
} else {
num_cards++;
}
}
i++;
}
TRACE("Number of succesfully initialised card : %d\n", (int)num_cards);
if (num_cards == 0) {
put_module(B_PCI_MODULE_NAME);
put_module(B_MPU_401_MODULE_NAME);
return ENODEV;
}
return B_OK;
}
static void
ice_1712_shutdown(ice1712 *ice)
void
ice1712HW_shutdown(ice1712 *ice)
{
delete_sem(ice->buffer_ready_sem);
remove_io_interrupt_handler(ice->irq, ice_1712_int, ice);
remove_io_interrupt_handler(ice->irq, ice1712HW_interrupt, ice);
if (ice->mem_id_pb != B_ERROR)
delete_area(ice->mem_id_pb);
@@ -463,58 +507,26 @@ ice_1712_shutdown(ice1712 *ice)
codec_write(ice, AK45xx_RESET_REGISTER, 0x00);
}
void
uninit_driver(void)
{
int ix, cnt = num_cards;
TRACE("@@uninit_driver()\n");
num_cards = 0;
for (ix = 0; ix < cnt; ix++) {
ice_1712_shutdown(&cards[ix]);
(*pci->unreserve_device)(cards[ix].info.bus,
cards[ix].info.device, cards[ix].info.function,
DRIVER_NAME, &cards[ix]);
}
memset(&cards, 0, sizeof(cards));
put_module(B_MPU_401_MODULE_NAME);
put_module(B_PCI_MODULE_NAME);
}
const char **
publish_devices(void)
{
int ix = 0;
TRACE("@@publish_devices()\n");
for (ix=0; names[ix]; ix++) {
TRACE("publish %s\n", names[ix]);
}
return (const char **)names;
}
//ICE1712 driver - Hook
//---------------------
static status_t
ice_1712_open(const char *name, uint32 flags, void **cookie)
ice1712Audio_open(const char *name, uint32 flags, void **cookie)
{
int ix;
ice1712 *card = NULL;
TRACE("**open()\n");
ITRACE("** open(): %s\n", name);
for (ix=0; ix<num_cards; ix++) {
for (ix = 0; ix<num_cards; ix++) {
if (!strcmp(cards[ix].name, name)) {
card = &cards[ix];
}
}
if (card == NULL) {
TRACE("open() card not found %s\n", name);
ITRACE("open() card not found %s\n", name);
for (ix=0; ix<num_cards; ix++) {
TRACE("open() card available %s\n", cards[ix].name);
ITRACE("open() card available %s\n", cards[ix].name);
}
return B_ERROR;
}
@@ -524,150 +536,151 @@ ice_1712_open(const char *name, uint32 flags, void **cookie)
static status_t
ice_1712_close(void *cookie)
ice1712Audio_close(void *cookie)
{
TRACE("**close()\n");
ITRACE("** close()\n");
return B_OK;
}
static status_t
ice_1712_free(void *cookie)
ice1712Audio_free(void *cookie)
{
TRACE("**free()\n");
ITRACE("** free()\n");
return B_OK;
}
static status_t
ice_1712_control(void *cookie, uint32 op, void *arg, size_t len)
ice1712Audio_control(void *cookie, uint32 op, void *arg, size_t len)
{
switch (op) {
case B_MULTI_GET_DESCRIPTION :
TRACE("B_MULTI_GET_DESCRIPTION\n");
return ice1712_get_description((ice1712 *)cookie,
ITRACE("B_MULTI_GET_DESCRIPTION\n");
return ice1712Get_Description((ice1712 *)cookie,
(multi_description*)arg);
case B_MULTI_GET_EVENT_INFO :
TRACE("B_MULTI_GET_EVENT_INFO\n");
ITRACE("B_MULTI_GET_EVENT_INFO\n");
return B_ERROR;
case B_MULTI_SET_EVENT_INFO :
TRACE("B_MULTI_SET_EVENT_INFO\n");
ITRACE("B_MULTI_SET_EVENT_INFO\n");
return B_ERROR;
case B_MULTI_GET_EVENT :
TRACE("B_MULTI_GET_EVENT\n");
ITRACE("B_MULTI_GET_EVENT\n");
return B_ERROR;
case B_MULTI_GET_ENABLED_CHANNELS :
TRACE("B_MULTI_GET_ENABLED_CHANNELS\n");
return ice1712_get_enabled_channels((ice1712*)cookie,
ITRACE("B_MULTI_GET_ENABLED_CHANNELS\n");
return ice1712Get_Channel((ice1712*)cookie,
(multi_channel_enable*)arg);
case B_MULTI_SET_ENABLED_CHANNELS :
TRACE("B_MULTI_SET_ENABLED_CHANNELS\n");
return ice1712_set_enabled_channels((ice1712*)cookie,
ITRACE("B_MULTI_SET_ENABLED_CHANNELS\n");
return ice1712Set_Channel((ice1712*)cookie,
(multi_channel_enable*)arg);
case B_MULTI_GET_GLOBAL_FORMAT :
TRACE("B_MULTI_GET_GLOBAL_FORMAT\n");
return ice1712_get_global_format((ice1712*)cookie,
ITRACE("B_MULTI_GET_GLOBAL_FORMAT\n");
return ice1712Get_Format((ice1712*)cookie,
(multi_format_info *)arg);
case B_MULTI_SET_GLOBAL_FORMAT :
TRACE("B_MULTI_SET_GLOBAL_FORMAT\n");
return ice1712_set_global_format((ice1712*)cookie,
ITRACE("B_MULTI_SET_GLOBAL_FORMAT\n");
return ice1712Set_Format((ice1712*)cookie,
(multi_format_info *)arg);
case B_MULTI_GET_CHANNEL_FORMATS :
TRACE("B_MULTI_GET_CHANNEL_FORMATS\n");
ITRACE("B_MULTI_GET_CHANNEL_FORMATS\n");
return B_ERROR;
case B_MULTI_SET_CHANNEL_FORMATS :
TRACE("B_MULTI_SET_CHANNEL_FORMATS\n");
ITRACE("B_MULTI_SET_CHANNEL_FORMATS\n");
return B_ERROR;
case B_MULTI_GET_MIX :
TRACE("B_MULTI_GET_MIX\n");
return ice1712_get_mix((ice1712*)cookie,
ITRACE("B_MULTI_GET_MIX\n");
return ice1712Get_MixValue((ice1712*)cookie,
(multi_mix_value_info *)arg);
case B_MULTI_SET_MIX :
TRACE("B_MULTI_SET_MIX\n");
return ice1712_set_mix((ice1712*)cookie,
ITRACE("B_MULTI_SET_MIX\n");
return ice1712Set_MixValue((ice1712*)cookie,
(multi_mix_value_info *)arg);
case B_MULTI_LIST_MIX_CHANNELS :
TRACE("B_MULTI_LIST_MIX_CHANNELS\n");
return ice1712_list_mix_channels((ice1712*)cookie,
ITRACE("B_MULTI_LIST_MIX_CHANNELS\n");
return ice1712Get_MixValueChannel((ice1712*)cookie,
(multi_mix_channel_info *)arg);
case B_MULTI_LIST_MIX_CONTROLS :
TRACE("B_MULTI_LIST_MIX_CONTROLS\n");
return ice1712_list_mix_controls((ice1712*)cookie,
ITRACE("B_MULTI_LIST_MIX_CONTROLS\n");
return ice1712Get_MixValueControls((ice1712*)cookie,
(multi_mix_control_info *)arg);
case B_MULTI_LIST_MIX_CONNECTIONS :
TRACE("B_MULTI_LIST_MIX_CONNECTIONS\n");
return ice1712_list_mix_connections((ice1712*)cookie,
ITRACE("B_MULTI_LIST_MIX_CONNECTIONS\n");
return ice1712Get_MixValueConnections((ice1712*)cookie,
(multi_mix_connection_info *)arg);
case B_MULTI_GET_BUFFERS :
TRACE("B_MULTI_GET_BUFFERS\n");
return ice1712_get_buffers((ice1712*)cookie,
ITRACE("B_MULTI_GET_BUFFERS\n");
return ice1712Buffer_Get((ice1712*)cookie,
(multi_buffer_list*)arg);
case B_MULTI_SET_BUFFERS :
TRACE("B_MULTI_SET_BUFFERS\n");
ITRACE("B_MULTI_SET_BUFFERS\n");
return B_ERROR;
case B_MULTI_SET_START_TIME :
TRACE("B_MULTI_SET_START_TIME\n");
ITRACE("B_MULTI_SET_START_TIME\n");
return B_ERROR;
case B_MULTI_BUFFER_EXCHANGE :
// TRACE("B_MULTI_BUFFER_EXCHANGE\n");
return ice1712_buffer_exchange((ice1712*)cookie,
// ITRACE("B_MULTI_BUFFER_EXCHANGE\n");
return ice1712Buffer_Exchange((ice1712*)cookie,
(multi_buffer_info *)arg);
case B_MULTI_BUFFER_FORCE_STOP :
TRACE("B_MULTI_BUFFER_FORCE_STOP\n");
return ice1712_buffer_force_stop((ice1712*)cookie);
ITRACE("B_MULTI_BUFFER_FORCE_STOP\n");
return ice1712Buffer_Stop((ice1712*)cookie);
case B_MULTI_LIST_EXTENSIONS :
TRACE("B_MULTI_LIST_EXTENSIONS\n");
ITRACE("B_MULTI_LIST_EXTENSIONS\n");
return B_ERROR;
case B_MULTI_GET_EXTENSION :
TRACE("B_MULTI_GET_EXTENSION\n");
ITRACE("B_MULTI_GET_EXTENSION\n");
return B_ERROR;
case B_MULTI_SET_EXTENSION :
TRACE("B_MULTI_SET_EXTENSION\n");
ITRACE("B_MULTI_SET_EXTENSION\n");
return B_ERROR;
case B_MULTI_LIST_MODES :
TRACE("B_MULTI_LIST_MODES\n");
ITRACE("B_MULTI_LIST_MODES\n");
return B_ERROR;
case B_MULTI_GET_MODE :
TRACE("B_MULTI_GET_MODE\n");
ITRACE("B_MULTI_GET_MODE\n");
return B_ERROR;
case B_MULTI_SET_MODE :
TRACE("B_MULTI_SET_MODE\n");
ITRACE("B_MULTI_SET_MODE\n");
return B_ERROR;
default :
TRACE("ERROR: unknown multi_control %#x\n", (int)op);
ITRACE("ERROR: unknown multi_control %#x\n", (int)op);
return B_ERROR;
}
}
static status_t
ice_1712_read(void *cookie, off_t position, void *buf, size_t *num_bytes)
ice1712Audio_read(void *cookie, off_t position, void *buf,
size_t *num_bytes)
{
TRACE("**read()\n");
ITRACE("** read()\n");
*num_bytes = 0;
return B_IO_ERROR;
}
static status_t
ice_1712_write(void *cookie, off_t position, const void *buffer,
ice1712Audio_write(void *cookie, off_t position, const void *buffer,
size_t *num_bytes)
{
TRACE("**write()\n");
ITRACE("** write()\n");
*num_bytes = 0;
return B_IO_ERROR;
}
device_hooks ice1712_hooks =
device_hooks ice1712Audio_hooks =
{
ice_1712_open,
ice_1712_close,
ice_1712_free,
ice_1712_control,
ice_1712_read,
ice_1712_write,
ice1712Audio_open,
ice1712Audio_close,
ice1712Audio_free,
ice1712Audio_control,
ice1712Audio_read,
ice1712Audio_write,
NULL,
NULL,
NULL,
@@ -675,46 +688,12 @@ device_hooks ice1712_hooks =
};
device_hooks ice1712_midi_hooks =
{
ice_1712_midi_open,
ice_1712_midi_close,
ice_1712_midi_free,
ice_1712_midi_control,
ice_1712_midi_read,
ice_1712_midi_write,
NULL,
NULL,
NULL,
NULL
};
//ICE1712 Drivers - Settings
//--------------------------
device_hooks *
find_device(const char * name)
{
int ix, midi;
TRACE("**find_device(%s)\n", name);
for (ix=0; ix < num_cards; ix++) {
for (midi = 0; midi < MAX_MIDI_INTERFACE; midi++) {
if (!strcmp(cards[ix].midi_interf[midi].name, name)) {
return &ice1712_midi_hooks;
}
}
if (!strcmp(cards[ix].name, name)) {
return &ice1712_hooks;
}
}
TRACE("!!! failed !!!\n");
return NULL;
}
status_t
load_settings(ice1712 *card)
ice1712Settings_load(ice1712 *card)
{
// get driver settings
void *settings_handle = load_driver_settings("ice1712.settings");
@@ -726,9 +705,9 @@ load_settings(ice1712 *card)
const char *item;
char *end;
item = get_driver_parameter(settings_handle, "buffer_size",
"512", "512");
if (item) {
item = get_driver_parameter(settings_handle,
"buffer_size", "512", "512");
if (item != NULL) {
uint32 value = strtoul(item, &end, 0);
if ((*end == '\0')
&& (value >= MIN_BUFFER_FRAMES)
@@ -745,7 +724,7 @@ load_settings(ice1712 *card)
status_t
apply_settings(ice1712 *card)
ice1712Settings_apply(ice1712 *card)
{
int i;
uint16 val, mt30 = 0;
@@ -758,7 +737,7 @@ apply_settings(ice1712 *card)
if (card->settings.playback[i].mute == true) {
val = (ICE1712_MUTE_VALUE << 0) | (ICE1712_MUTE_VALUE << 8);
} else {
unsigned char volume = card->settings.playback[i].volume / -1.5;
uint8 volume = card->settings.playback[i].volume / -1.5;
if (i & 1) {//a right channel
val = ICE1712_MUTE_VALUE << 0; //Mute left volume
val |= volume << 8;
@@ -769,7 +748,7 @@ apply_settings(ice1712 *card)
}
write_mt_uint16(card, MT_LR_VOLUME_CONTROL, val);
TRACE_VV("Apply Settings %d : 0x%x\n", i, val);
ITRACE_VV("Apply Settings %d : 0x%x\n", i, val);
}
for (i = 0; i < ICE1712_HARDWARE_VOLUME; i++) {
@@ -791,30 +770,30 @@ apply_settings(ice1712 *card)
}
write_mt_uint16(card, MT_LR_VOLUME_CONTROL, val);
TRACE_VV("Apply Settings %d : 0x%x\n", i, val);
ITRACE_VV("Apply Settings %d : 0x%x\n", i, val);
}
//Analog output selection
for (i = 0; i < 4; i++) {
uint8 out = card->settings.output[i];
if (out == 0) {
TRACE_VV("Output %d is haiku output\n", i);
ITRACE_VV("Output %d is haiku output\n", i);
//Nothing to do
} else if (out <= (card->config.nb_ADC / 2)) {
uint8 mt34_c;
out--;
TRACE_VV("Output %d is input %d\n", i, out);
ITRACE_VV("Output %d is input %d\n", i, out);
mt34_c = (out * 2);
mt34_c |= (out * 2 + 1) << 4;
mt30 |= 0x0202 << (2*i);
mt30 |= mt34_c << (8*i);
mt30 |= 0x0202 << (2 * i);
mt30 |= mt34_c << (8 * i);
} else if (out == ((card->config.nb_ADC / 2) + 1)
&& (card->config.spdif & SPDIF_IN_PRESENT) != 0) {
TRACE_VV("Output %d is digital input\n", i);
mt30 |= 0x0303 << (2*i);
mt34 |= 0x80 << (8*i);
ITRACE_VV("Output %d is digital input\n", i);
mt30 |= 0x0303 << (2 * i);
mt34 |= 0x80 << (8 * i);
} else {
TRACE_VV("Output %d is digital Mixer\n", i);
ITRACE_VV("Output %d is digital Mixer\n", i);
mt30 |= 0x0101;
}
}
@@ -826,26 +805,25 @@ apply_settings(ice1712 *card)
uint16 mt32 = 0;
uint8 out = card->settings.output[4];
if (out == 0) {
TRACE_VV("Digital output is haiku output\n");
ITRACE_VV("Digital output is haiku output\n");
//Nothing to do
} else if (out <= (card->config.nb_ADC / 2)) {
out--;
TRACE_VV("Digital output is input %d\n", out);
ITRACE_VV("Digital output is input %d\n", out);
mt32 |= 0x0202;
mt32 |= (out * 2) << 8;
mt32 |= (out * 2 + 1) << 12;
} else if (out == ((card->config.nb_ADC / 2) + 1)
&& (card->config.spdif & SPDIF_IN_PRESENT) != 0) {
TRACE_VV("Digital output is digital input\n");
ITRACE_VV("Digital output is digital input\n");
mt32 |= 0x800F;
} else {
TRACE_VV("Digital output is digital Mixer\n");
ITRACE_VV("Digital output is digital Mixer\n");
mt32 |= 0x0005;
}
write_mt_uint16(card, MT_ROUTING_CONTROL_SPDOUT, mt32);
}
return B_OK;
}
src/add-ons/kernel/drivers/audio/ice1712/ice1712.h
+79 -91
View File
@@ -1,30 +1,30 @@
/*
* ice1712 BeOS/Haiku Driver for VIA - VT1712 Multi Channel Audio Controller
* Copyright 2004-2015 Haiku, Inc. All rights reserved.
* Distributed under the terms of the MIT License.
*
* Copyright (c) 2002, Jerome Duval ([email protected])
* Copyright (c) 2003, Marcus Overhagen ([email protected])
* Copyright (c) 2007, Jerome Leveque ([email protected])
*
* All rights reserved
* Distributed under the terms of the MIT license.
* Authors:
* Jérôme Duval, [email protected]
* Marcus Overhagen, [email protected]
* Jérôme Lévêque, [email protected]
*/
#ifndef _ICE1712_H_
#define _ICE1712_H_
#include "debug.h"
#include "hmulti_audio.h"
#include <PCI.h>
#include <KernelExport.h>
#define DRIVER_NAME "ice1712"
#define VERSION "0.5"
#define VERSION "0.6"
#define ICE1712_VENDOR_ID 0x1412
#define ICE1712_DEVICE_ID 0x1712
#define ICE1712_VENDOR_ID 0x1412
#define ICE1712_DEVICE_ID 0x1712
typedef enum product_t {
typedef enum ice1712Product {
ICE1712_SUBDEVICE_DELTA1010 = 0x121430d6,
ICE1712_SUBDEVICE_DELTADIO2496 = 0x121431d6,
ICE1712_SUBDEVICE_DELTA66 = 0x121432d6,
@@ -33,10 +33,11 @@ typedef enum product_t {
ICE1712_SUBDEVICE_DELTA410 = 0x121438d6,
ICE1712_SUBDEVICE_DELTA1010LT = 0x12143bd6,
ICE1712_SUBDEVICE_VX442 = 0x12143cd6,
} product_t;
} ice1712Product;
#define NUM_CARDS 4
#define MAX_ADC 12 // + the output of the Digital mixer
#define MAX_ADC 12
// 5 stereo output + the Digital mixer
#define MAX_DAC 10
#define MAX_MIDI_INTERFACE 2
#define SWAPPING_BUFFERS 2
@@ -45,7 +46,7 @@ typedef enum product_t {
#define MAX_BUFFER_FRAMES 2048
#define ICE1712_HARDWARE_VOLUME 10
#define ICE1712_MUTE_VALUE 0x7F
#define ICE1712_MUTE_VALUE 0x7F
#define PLAYBACK_BUFFER_SIZE (MAX_BUFFER_FRAMES * MAX_DAC * SAMPLE_SIZE)
#define RECORD_BUFFER_SIZE (MAX_BUFFER_FRAMES * MAX_ADC * SAMPLE_SIZE)
@@ -68,68 +69,62 @@ typedef enum product_t {
struct ice1712;
typedef struct _midi_dev {
struct ice1712 *card;
void *mpu401device;
uint8 int_mask;
char name[64];
} midi_dev;
void ice_1712_midi_interrupt_op(int32 op, void *data);
status_t ice_1712_midi_open(const char *name,
uint32 flags, void **cookie);
status_t ice_1712_midi_close(void *cookie);
status_t ice_1712_midi_free(void *cookie);
status_t ice_1712_midi_control(void *cookie,
uint32 op, void *data, size_t len);
status_t ice_1712_midi_read(void *cookie,
off_t pos, void *data, size_t *len);
status_t ice_1712_midi_write(void *cookie,
off_t pos, const void *data, size_t *len);
typedef struct ice1712Midi {
struct ice1712 *card;
void *mpu401device;
uint8 int_mask;
char name[64];
} ice1712Midi;
typedef struct _codecCommLines
{
uint8 clock;
uint8 data_in;
uint8 data_out;
uint8 cs_mask; //a Mask for removing all Chip select
uint8 reserved[4];
uint8 clock;
uint8 data_in;
uint8 data_out;
uint8 cs_mask;
//a Mask for removing all Chip select
} codecCommLines;
typedef struct channel_volume
typedef struct ice1712Volume
{
float volume;
bool mute;
} channel_volume;
} ice1712Volume;
typedef struct ice1712_settings
typedef struct ice1712Settings
{
channel_volume playback[ICE1712_HARDWARE_VOLUME];
channel_volume record[ICE1712_HARDWARE_VOLUME];
ice1712Volume playback[ICE1712_HARDWARE_VOLUME];
ice1712Volume record[ICE1712_HARDWARE_VOLUME];
uint32 bufferSize;
//General Settings
uint8 clock; //an index
uint8 clock; //an index
//S/PDif Settings
uint8 outFormat; //an index
uint8 emphasis; //an index
uint8 copyMode; //an index
uint8 outFormat; //an index
uint8 emphasis; //an index
uint8 copyMode; //an index
//Output settings
uint8 output[5]; //an index
uint8 output[5]; //an index
uint8 reserved[32];
} ice1712_settings;
} ice1712Settings;
typedef struct ice1712_hconfig
typedef struct ice1712HW
{
int8 nb_ADC; //Mono Channel
int8 nb_DAC; //Mono Channel
int8 nb_ADC; //Mono Channel
int8 nb_DAC; //Mono Channel
int8 nb_MPU401;
int8 spdif;
} ice1712_hconfig;
//in the format of the register
uint8 samplingRate;
uint32 lockSource;
ice1712Product product;
} ice1712HW;
typedef struct ice1712
{
@@ -137,7 +132,7 @@ typedef struct ice1712
pci_info info;
char name[128];
midi_dev midi_interf[MAX_MIDI_INTERFACE];
ice1712Midi midiItf[MAX_MIDI_INTERFACE];
uint32 Controller; //PCI_10
uint32 DDMA; //PCI_14
@@ -146,8 +141,6 @@ typedef struct ice1712
uint8 eeprom_data[32];
product_t product;
//We hope all manufacturers will use same
//communication lines for speaking with codec
codecCommLines CommLines;
@@ -159,29 +152,22 @@ typedef struct ice1712
//Output
area_id mem_id_pb;
void *phys_addr_pb, *log_addr_pb;
physical_entry phys_pb;
addr_t log_addr_pb;
uint8 total_output_channels;
//Input
area_id mem_id_rec;
void *phys_addr_rec, *log_addr_rec;
physical_entry phys_rec;
addr_t log_addr_rec;
uint8 total_input_channels;
sem_id buffer_ready_sem;
uint8 sampling_rate; //in the format of the register
uint32 lock_source;
ice1712_hconfig config;
ice1712_settings settings;
ice1712HW config;
ice1712Settings settings;
} ice1712;
status_t apply_settings(ice1712 *card);
//For midi.c
extern int32 num_cards;
extern ice1712 cards[NUM_CARDS];
//CSS_INTERRUPT_MASK
#define CCS_INTERRUPT_MIDI_1 0x80
#define CCS_INTERRUPT_MIDI_2 0x20
@@ -227,7 +213,7 @@ extern ice1712 cards[NUM_CARDS];
#define VX442_CS_MASK 0x70 // Chip Select Mask
#define GPIO_I2C_DELAY 5 //Clock Delay for writing
//I2C data throw GPIO
//I2C data throw GPIO
//Register definition for the AK45xx codec (xx = 24 or 28)
#define AK45xx_CHIP_ADDRESS 0x02 //Chip address of the codec
@@ -271,25 +257,27 @@ extern ice1712 cards[NUM_CARDS];
*/
//This map comes from ALSA sound drivers
#define E2PROM_MAP_SUBVENDOR_LOW 0x00
#define E2PROM_MAP_SUBVENDOR_HIGH 0x01
#define E2PROM_MAP_SUBDEVICE_LOW 0x02
#define E2PROM_MAP_SUBDEVICE_HIGH 0x03
#define E2PROM_MAP_SIZE 0x04
#define E2PROM_MAP_VERSION 0x05
#define E2PROM_MAP_CONFIG 0x06
#define E2PROM_MAP_ACL 0x07
#define E2PROM_MAP_I2S 0x08
#define E2PROM_MAP_SPDIF 0x09
#define E2PROM_MAP_GPIOMASK 0x0A
#define E2PROM_MAP_GPIOSTATE 0x0B
#define E2PROM_MAP_GPIODIR 0x0C
#define E2PROM_MAP_AC97MAIN 0x0D
#define E2PROM_MAP_AC97PCM 0x0F
#define E2PROM_MAP_AC97REC 0x11
#define E2PROM_MAP_AC97REC_SOURCE 0x13
#define E2PROM_MAP_DAC_ID 0x14
#define E2PROM_MAP_ADC_ID 0x18
#define E2PROM_MAP_EXTRA 0x1C
typedef enum ice1712EEprom {
E2PROM_MAP_SUBVENDOR_LOW = 0x00,
E2PROM_MAP_SUBVENDOR_HIGH,
E2PROM_MAP_SUBDEVICE_LOW,
E2PROM_MAP_SUBDEVICE_HIGH,
E2PROM_MAP_SIZE,
E2PROM_MAP_VERSION,
E2PROM_MAP_CONFIG,
E2PROM_MAP_ACL,
E2PROM_MAP_I2S,
E2PROM_MAP_SPDIF,
E2PROM_MAP_GPIOMASK,
E2PROM_MAP_GPIOSTATE,
E2PROM_MAP_GPIODIR,
E2PROM_MAP_AC97MAIN,
E2PROM_MAP_AC97PCM = 0x0F,
E2PROM_MAP_AC97REC = 0x11,
E2PROM_MAP_AC97REC_SOURCE = 0x13,
E2PROM_MAP_DAC_ID = 0x14,
E2PROM_MAP_ADC_ID = 0x18,
E2PROM_MAP_EXTRA = 0x1C
} ice1712EEprom;
#endif
src/add-ons/kernel/drivers/audio/ice1712/ice1712_reg.h
+110 -147
View File
@@ -1,167 +1,130 @@
/*
* ice1712 BeOS/Haiku Driver for VIA - VT1712 Multi Channel Audio Controller
* Copyright 2004-2015 Haiku, Inc. All rights reserved.
* Distributed under the terms of the MIT License.
*
* Copyright (c) 2007, Jerome Leveque ([email protected])
*
* All rights reserved
* Distributed under the terms of the MIT license.
* Authors:
* Jérôme Duval, [email protected]
* Marcus Overhagen, [email protected]
* Jérôme Lévêque, [email protected]
*/
#ifndef _ICE1712_REG_H_
#define _ICE1712_REG_H_
//------------------------------------------------------
//------------------------------------------------------
//PCI Interface and Configuration Registers (Page 3.1)
//Table 3.1
/*
#define PCI_VENDOR_ID 0x00 //2 bytes
#define PCI_DEVICE_ID 0x02 //2 bytes
#define PCI_COMMAND 0x04 //2 bytes
#define PCI_DEVICE_STATUS 0x06 //2 bytes
#define PCI_REVISION_ID 0x08 //1 byte
#define PCI_CLASS_CODE 0x0A //2 bytes
#define PCI_LATENCY_TIMER 0x0D //1 byte
#define PCI_HEADER_TYPE 0x0E //1 byte
#define PCI_BIST 0x0F //1 byte
#define PCI_CONTROLLER_BASE_AD 0x10 //4 bytes
#define PCI_DDMA_BASE_AD 0x14 //4 bytes
#define PCI_DMA_BASE_AD 0x18 //4 bytes
#define PCI_MULTI_BASE_AD 0x1C //4 bytes
#define PCI_SUB_VENDOR_ID 0x2C //2 bytes
#define PCI_SUB_SYSTEM_ID 0x2E //2 bytes
#define PCI_CAPABILITY_POINTER 0x34 //4 bytes
#define PCI_INT_PIN_LINE 0x3C //2 bytes
#define PCI_LATENCY_GRANT 0x3E //2 bytes
#define PCI_LEGACY_AUDIO_CONTROL 0x40 //2 bytes
#define PCI_LEGACY_CONF_CONTROL 0x42 //2 bytes
#define PCI_HARD_CONF_CONTROL 0x60 //4 bytes
#define PCI_CAPABILITY_ID 0x80 //1 byte
#define PCI_NEXT_ITEM_POINTER 0x81 //1 byte
#define PCI_POWER_CAPABILITY 0x82 //2 bytes
#define PCI_POWER_CONTROL_STATUS 0x84 //2 bytes
#define PCI_PMCSR_EXT_DATA 0x86 //2 bytes
*/
//------------------------------------------------------
//------------------------------------------------------
#define PCI_VENDOR_ID 0x00 //2 bytes
#define PCI_DEVICE_ID 0x02 //2 bytes
#define PCI_COMMAND 0x04 //2 bytes
#define PCI_DEVICE_STATUS 0x06 //2 bytes
#define PCI_REVISION_ID 0x08 //1 byte
#define PCI_CLASS_CODE 0x0A //2 bytes
#define PCI_LATENCY_TIMER 0x0D //1 byte
#define PCI_HEADER_TYPE 0x0E //1 byte
#define PCI_BIST 0x0F //1 byte
#define PCI_CONTROLLER_BASE_AD 0x10 //4 bytes
#define PCI_DDMA_BASE_AD 0x14 //4 bytes
#define PCI_DMA_BASE_AD 0x18 //4 bytes
#define PCI_MULTI_BASE_AD 0x1C //4 bytes
#define PCI_SUB_VENDOR_ID 0x2C //2 bytes
#define PCI_SUB_SYSTEM_ID 0x2E //2 bytes
#define PCI_CAPABILITY_POINTER 0x34 //4 bytes
#define PCI_INT_PIN_LINE 0x3C //2 bytes
#define PCI_LATENCY_GRANT 0x3E //2 bytes
#define PCI_LEGACY_AUDIO_CONTROL 0x40 //2 bytes
#define PCI_LEGACY_CONF_CONTROL 0x42 //2 bytes
#define PCI_HARD_CONF_CONTROL 0x60 //4 bytes
#define PCI_CAPABILITY_ID 0x80 //1 byte
#define PCI_NEXT_ITEM_POINTER 0x81 //1 byte
#define PCI_POWER_CAPABILITY 0x82 //2 bytes
#define PCI_POWER_CONTROL_STATUS 0x84 //2 bytes
#define PCI_PMCSR_EXT_DATA 0x86 //2 bytes
//CCSxx Controller Register Map (Page 4.3)
//Table 4.2
#define CCS_CONTROL_STATUS 0x00 //1 byte
#define CCS_INTERRUPT_MASK 0x01 //1 byte
#define CCS_INTERRUPT_STATUS 0x02 //1 byte
#define CCS_CCI_INDEX 0x03 //1 byte
#define CCS_CCI_DATA 0x04 //1 byte
#define CCS_NMI_STATUS_1 0x05 //1 byte
#define CCS_NMI_DATA 0x06 //1 byte
#define CCS_NMI_INDEX 0x07 //1 byte
#define CCS_CONS_AC97_INDEX 0x08 //1 byte
#define CCS_CONS_AC97_COMMAND_STATUS 0x09 //1 byte
#define CCS_CONS_AC97_DATA 0x0A //2 bytes
#define CCS_MIDI_1_DATA 0x0C //1 byte
#define CCS_MIDI_1_COMMAND_STATUS 0x0D //1 byte
#define CCS_NMI_STATUS_2 0x0E //1 byte
#define CCS_GAME_PORT 0x0F //1 byte
#define CCS_I2C_DEV_ADDRESS 0x10 //1 byte
#define CCS_I2C_BYTE_ADDRESS 0x11 //1 byte
#define CCS_I2C_DATA 0x12 //1 byte
#define CCS_I2C_CONTROL_STATUS 0x13 //1 byte
#define CCS_CONS_DMA_BASE_ADDRESS 0x14 //4 bytes
#define CCS_CONS_DMA_COUNT_ADDRESS 0x18 //2 bytes
#define CCS_SERR_SHADOW 0x1B //1 byte
#define CCS_MIDI_2_DATA 0x1C //1 byte
#define CCS_MIDI_2_COMMAND_STATUS 0x1D //1 byte
#define CCS_TIMER 0x1E //2 bytes
//------------------------------------------------------
//------------------------------------------------------
#define CCS_CONTROL_STATUS 0x00 //1 byte
#define CCS_INTERRUPT_MASK 0x01 //1 byte
#define CCS_INTERRUPT_STATUS 0x02 //1 byte
#define CCS_CCI_INDEX 0x03 //1 byte
#define CCS_CCI_DATA 0x04 //1 byte
#define CCS_NMI_STATUS_1 0x05 //1 byte
#define CCS_NMI_DATA 0x06 //1 byte
#define CCS_NMI_INDEX 0x07 //1 byte
#define CCS_CONS_AC97_INDEX 0x08 //1 byte
#define CCS_CONS_AC97_COMMAND_STATUS 0x09 //1 byte
#define CCS_CONS_AC97_DATA 0x0A //2 bytes
#define CCS_MIDI_1_DATA 0x0C //1 byte
#define CCS_MIDI_1_COMMAND_STATUS 0x0D //1 byte
#define CCS_NMI_STATUS_2 0x0E //1 byte
#define CCS_GAME_PORT 0x0F //1 byte
#define CCS_I2C_DEV_ADDRESS 0x10 //1 byte
#define CCS_I2C_BYTE_ADDRESS 0x11 //1 byte
#define CCS_I2C_DATA 0x12 //1 byte
#define CCS_I2C_CONTROL_STATUS 0x13 //1 byte
#define CCS_CONS_DMA_BASE_ADDRESS 0x14 //4 bytes
#define CCS_CONS_DMA_COUNT_ADDRESS 0x18 //2 bytes
#define CCS_SERR_SHADOW 0x1B //1 byte
#define CCS_MIDI_2_DATA 0x1C //1 byte
#define CCS_MIDI_2_COMMAND_STATUS 0x1D //1 byte
#define CCS_TIMER 0x1E //2 bytes
//Controller Indexed Register (Page 4.12)
#define CCI_PB_TERM_COUNT_HI 0x00 //1 byte
#define CCI_PB_TERM_COUNT_LO 0x01 //1 byte
#define CCI_PB_CONTROL 0x02 //1 byte
#define CCI_PB_LEFT_VOLUME 0x03 //1 byte
#define CCI_PB_RIGHT_VOLUME 0x04 //1 byte
#define CCI_SOFT_VOLUME 0x05 //1 byte
#define CCI_PB_SAMPLING_RATE_LO 0x06 //1 byte
#define CCI_PB_SAMPLING_RATE_MI 0x07 //1 byte
#define CCI_PB_SAMPLING_RATE_HI 0x08 //1 byte
#define CCI_REC_TERM_COUNT_HI 0x10 //1 byte
#define CCI_REC_TERM_COUNT_LO 0x11 //1 byte
#define CCI_REC_CONTROL 0x12 //1 byte
#define CCI_GPIO_DATA 0x20 //1 byte
#define CCI_GPIO_WRITE_MASK 0x21 //1 byte
#define CCI_GPIO_DIRECTION_CONTROL 0x22 //1 byte
#define CCI_CONS_POWER_DOWN 0x30 //1 byte
#define CCI_MULTI_POWER_DOWN 0x31 //1 byte
//------------------------------------------------------
//------------------------------------------------------
#define CCI_PB_TERM_COUNT_HI 0x00 //1 byte
#define CCI_PB_TERM_COUNT_LO 0x01 //1 byte
#define CCI_PB_CONTROL 0x02 //1 byte
#define CCI_PB_LEFT_VOLUME 0x03 //1 byte
#define CCI_PB_RIGHT_VOLUME 0x04 //1 byte
#define CCI_SOFT_VOLUME 0x05 //1 byte
#define CCI_PB_SAMPLING_RATE_LO 0x06 //1 byte
#define CCI_PB_SAMPLING_RATE_MI 0x07 //1 byte
#define CCI_PB_SAMPLING_RATE_HI 0x08 //1 byte
#define CCI_REC_TERM_COUNT_HI 0x10 //1 byte
#define CCI_REC_TERM_COUNT_LO 0x11 //1 byte
#define CCI_REC_CONTROL 0x12 //1 byte
#define CCI_GPIO_DATA 0x20 //1 byte
#define CCI_GPIO_WRITE_MASK 0x21 //1 byte
#define CCI_GPIO_DIRECTION_CONTROL 0x22 //1 byte
#define CCI_CONS_POWER_DOWN 0x30 //1 byte
#define CCI_MULTI_POWER_DOWN 0x31 //1 byte
//Consumer Section DMA Channel Registers (Page 4.20)
//Table 4.4
#define DS_DMA_INT_MASK 0x00 //2 bytes
#define DS_DMA_INT_STATUS 0x02 //2 bytes
#define DS_CHANNEL_DATA 0x04 //4 bytes
#define DS_CHANNEL_INDEX 0x08 //1 byte
//------------------------------------------------------
//------------------------------------------------------
#define DS_DMA_INT_MASK 0x00 //2 bytes
#define DS_DMA_INT_STATUS 0x02 //2 bytes
#define DS_CHANNEL_DATA 0x04 //4 bytes
#define DS_CHANNEL_INDEX 0x08 //1 byte
//Professional Multi-Track Control Registers (Page 4.24)
//Table 4.7
#define MT_DMA_INT_MASK_STATUS 0x00 //1 byte
#define MT_SAMPLING_RATE_SELECT 0x01 //1 byte
#define MT_I2S_DATA_FORMAT 0x02 //1 byte
#define MT_PROF_AC97_INDEX 0x04 //1 byte
#define MT_PROF_AC97_COMMAND_STATUS 0x05 //1 byte
#define MT_PROF_AC97_DATA 0x06 //2 bytes
#define MT_PROF_PB_DMA_BASE_ADDRESS 0x10 //4 bytes
#define MT_PROF_PB_DMA_COUNT_ADDRESS 0x14 //2 bytes
#define MT_PROF_PB_DMA_TERM_COUNT 0x16 //2 bytes
#define MT_PROF_PB_CONTROL 0x18 //1 byte
#define MT_PROF_REC_DMA_BASE_ADDRESS 0x20 //4 bytes
#define MT_PROF_REC_DMA_COUNT_ADDRESS 0x24 //2 bytes
#define MT_PROF_REC_DMA_TERM_COUNT 0x26 //2 bytes
#define MT_PROF_REC_CONTROL 0x28 //1 byte
#define MT_ROUTING_CONTROL_PSDOUT 0x30 //2 bytes
#define MT_ROUTING_CONTROL_SPDOUT 0x32 //2 bytes
#define MT_CAPTURED_DATA 0x34 //4 bytes
#define MT_LR_VOLUME_CONTROL 0x38 //2 bytes
#define MT_VOLUME_CONTROL_CHANNEL_INDEX 0x3A //1 byte
#define MT_VOLUME_CONTROL_RATE 0x3B //1 byte
#define MT_MIXER_MONITOR_RETURN 0x3C //1 byte
#define MT_PEAK_METER_INDEX 0x3E //1 byte
#define MT_PEAK_METER_DATA 0x3F //1 byte
//------------------------------------------------------
//------------------------------------------------------
#define I2C_EEPROM_ADDRESS_READ 0xA0 //1010 0000
#define I2C_EEPROM_ADDRESS_WRITE 0xA1 //1010 0001
//------------------------------------------------------
//------------------------------------------------------
#define SPDIF_STEREO_IN 0x02 //0000 0010
#define SPDIF_STEREO_OUT 0x01 //0000 0001
//------------------------------------------------------
//------------------------------------------------------
#define MT_DMA_INT_MASK_STATUS 0x00 //1 byte
#define MT_SAMPLING_RATE_SELECT 0x01 //1 byte
#define MT_I2S_DATA_FORMAT 0x02 //1 byte
#define MT_PROF_AC97_INDEX 0x04 //1 byte
#define MT_PROF_AC97_COMMAND_STATUS 0x05 //1 byte
#define MT_PROF_AC97_DATA 0x06 //2 bytes
#define MT_PROF_PB_DMA_BASE_ADDRESS 0x10 //4 bytes
#define MT_PROF_PB_DMA_COUNT_ADDRESS 0x14 //2 bytes
#define MT_PROF_PB_DMA_TERM_COUNT 0x16 //2 bytes
#define MT_PROF_PB_CONTROL 0x18 //1 byte
#define MT_PROF_REC_DMA_BASE_ADDRESS 0x20 //4 bytes
#define MT_PROF_REC_DMA_COUNT_ADDRESS 0x24 //2 bytes
#define MT_PROF_REC_DMA_TERM_COUNT 0x26 //2 bytes
#define MT_PROF_REC_CONTROL 0x28 //1 byte
#define MT_ROUTING_CONTROL_PSDOUT 0x30 //2 bytes
#define MT_ROUTING_CONTROL_SPDOUT 0x32 //2 bytes
#define MT_CAPTURED_DATA 0x34 //4 bytes
#define MT_LR_VOLUME_CONTROL 0x38 //2 bytes
#define MT_VOLUME_CONTROL_CHANNEL_INDEX 0x3A //1 byte
#define MT_VOLUME_CONTROL_RATE 0x3B //1 byte
#define MT_MIXER_MONITOR_RETURN 0x3C //1 byte
#define MT_PEAK_METER_INDEX 0x3E //1 byte
#define MT_PEAK_METER_DATA 0x3F //1 byte
//------------------------------------------------------
//------------------------------------------------------
#define I2C_EEPROM_ADDRESS_READ 0xA0 //1010 0000
#define I2C_EEPROM_ADDRESS_WRITE 0xA1 //1010 0001
//------------------------------------------------------
//------------------------------------------------------
//------------------------------------------------------
//------------------------------------------------------
//------------------------------------------------------
//------------------------------------------------------
//------------------------------------------------------
//------------------------------------------------------
//------------------------------------------------------
//------------------------------------------------------
//------------------------------------------------------
//------------------------------------------------------
//------------------------------------------------------
//------------------------------------------------------
//------------------------------------------------------
//------------------------------------------------------
#define SPDIF_STEREO_IN 0x02 //0000 0010
#define SPDIF_STEREO_OUT 0x01 //0000 0001
#endif
src/add-ons/kernel/drivers/audio/ice1712/io.c → src/add-ons/kernel/drivers/audio/ice1712/io.cpp
+65 -55
View File
@@ -1,14 +1,14 @@
/*
* ice1712 BeOS/Haiku Driver for VIA - VT1712 Multi Channel Audio Controller
* Copyright 2004-2015 Haiku, Inc. All rights reserved.
* Distributed under the terms of the MIT License.
*
* Copyright (c) 2002, Jerome Duval (jerome.duval@free.fr)
* Copyright (c) 2003, Marcus Overhagen (marcus@overhagen.de)
* Copyright (c) 2007, Jerome Leveque (leveque.jerome@neuf.fr)
*
* All rights reserved
* Distributed under the terms of the MIT license.
* Authors:
* Jérôme Duval, jerome.duval@free.fr
* Marcus Overhagen, marcus@overhagen.de
* Jérôme Lévêque, leveque.jerome@gmail.com
*/
#include "io.h"
#include "ice1712_reg.h"
#include "debug.h"
@@ -16,24 +16,23 @@
extern pci_module_info *pci;
static void ak45xx_write_gpio(ice1712 *ice, uint8 reg_addr,
uint8 data, uint8 chip_select, uint8 invert_cs);
uint8 data, uint8 chip_select, uint8 invert_cs);
static void cs84xx_write_gpio(ice1712 *ice, uint8 reg_addr,
uint8 data, uint8 chip_select, uint8 invert_cs);
uint8 data, uint8 chip_select, uint8 invert_cs);
static uint8 ak45xx_read_gpio(ice1712 *ice, uint8 reg_addr,
uint8 chip_select, uint8 invert_cs)
{return 0;} //Unimplemented
uint8 chip_select, uint8 invert_cs)
{return 0;} //Unimplemented
static uint8 cs84xx_read_gpio(ice1712 *ice, uint8 reg_addr,
uint8 chip_select, uint8 invert_cs);
uint8 chip_select, uint8 invert_cs);
static void write_gpio_byte(ice1712 *ice, uint8 data, uint8 gpio_data);
static uint8 read_gpio_byte(ice1712 *ice, uint8 gpio_data);
//Address are [PCI_10] + xx
uint8
read_ccs_uint8(ice1712 *ice, int8 regno)
{
@@ -91,10 +90,8 @@ write_cci_uint8(ice1712 *ice, int8 index, uint8 value)
write_ccs_uint8(ice, CCS_CCI_DATA, value);
};
//--------------------------------------------------
//--------------------------------------------------
//Address are [PCI_14] + xx
//Address are [PCI_14] + xx
uint8
read_ddma_uint8(ice1712 *ice, int8 regno)
{
@@ -137,8 +134,6 @@ write_ddma_uint32(ice1712 *ice, int8 regno, uint32 value)
};
//--------------------------------------------------
//--------------------------------------------------
//Address are [PCI_18] + x
uint8
read_ds_uint8(ice1712 *ice, int8 regno)
@@ -187,7 +182,7 @@ read_ds_channel_data(ice1712 *ice, uint8 channel, ds8_register index)
{
uint8 ds8_channel_index = channel << 4 | index;
write_ds_uint8(ice, DS_CHANNEL_INDEX, ds8_channel_index);
write_ds_uint8(ice, DS_CHANNEL_INDEX, ds8_channel_index);
return read_ds_uint32(ice, DS_CHANNEL_DATA);
}
@@ -198,60 +193,60 @@ write_ds_channel_data(ice1712 *ice, uint8 channel, ds8_register index,
{
uint8 ds8_channel_index = channel << 4 | index;
write_ds_uint8(ice, DS_CHANNEL_INDEX, ds8_channel_index);
write_ds_uint8(ice, DS_CHANNEL_INDEX, ds8_channel_index);
write_ds_uint32(ice, DS_CHANNEL_DATA, data);
}
//--------------------------------------------------
//--------------------------------------------------
//Address are [PCI_1C] + xx
uint8
read_mt_uint8(ice1712 *ice, int8 regno)
read_mt_uint8(ice1712 *ice, int8 regno)
{
return pci->read_io_8(ice->Multi_Track + regno);
return pci->read_io_8(ice->Multi_Track + regno);
};
uint16
read_mt_uint16(ice1712 *ice, int8 regno)
read_mt_uint16(ice1712 *ice, int8 regno)
{
return pci->read_io_16(ice->Multi_Track + regno);
return pci->read_io_16(ice->Multi_Track + regno);
};
uint32
read_mt_uint32(ice1712 *ice, int8 regno)
read_mt_uint32(ice1712 *ice, int8 regno)
{
return pci->read_io_32(ice->Multi_Track + regno);
};
void
write_mt_uint8(ice1712 *ice, int8 regno, uint8 value)
write_mt_uint8(ice1712 *ice, int8 regno, uint8 value)
{
pci->write_io_8(ice->Multi_Track + regno, value);
};
void
write_mt_uint16(ice1712 *ice, int8 regno, uint16 value)
write_mt_uint16(ice1712 *ice, int8 regno, uint16 value)
{
pci->write_io_16(ice->Multi_Track + regno, value);
};
void
write_mt_uint32(ice1712 *ice, int8 regno, uint32 value)
write_mt_uint32(ice1712 *ice, int8 regno, uint32 value)
{
pci->write_io_32(ice->Multi_Track + regno, value);
};
/*
* return -1 if error else return an uint8
*/
int16
read_i2c(ice1712 *ice, uint8 dev_addr, uint8 byte_addr)
{//return -1 if error else return an uint8
{
if (read_ccs_uint8(ice, CCS_I2C_CONTROL_STATUS) != 0x80)
return -1;
write_ccs_uint8(ice, CCS_I2C_BYTE_ADDRESS, byte_addr);
@@ -261,9 +256,12 @@ read_i2c(ice1712 *ice, uint8 dev_addr, uint8 byte_addr)
}
/*
* return -1 if error else return 0
*/
int16
write_i2c(ice1712 *ice, uint8 dev_addr, uint8 byte_addr, uint8 value)
{//return -1 if error else return 0
{
if (read_ccs_uint8(ice, CCS_I2C_CONTROL_STATUS) != 0x80)
return -1;
@@ -302,11 +300,13 @@ int16 read_eeprom(ice1712 *ice, uint8 eeprom[32])
void
codec_write(ice1712 *ice, uint8 reg_addr, uint8 data)
{
switch (ice->product) {
switch (ice->config.product) {
case ICE1712_SUBDEVICE_DELTA66:
case ICE1712_SUBDEVICE_DELTA44:
ak45xx_write_gpio(ice, reg_addr, data, DELTA66_CODEC_CS_0, 0);
ak45xx_write_gpio(ice, reg_addr, data, DELTA66_CODEC_CS_1, 0);
ak45xx_write_gpio(ice, reg_addr, data,
DELTA66_CODEC_CS_0, 0);
ak45xx_write_gpio(ice, reg_addr, data,
DELTA66_CODEC_CS_1, 0);
break;
case ICE1712_SUBDEVICE_DELTA410:
case ICE1712_SUBDEVICE_AUDIOPHILE_2496:
@@ -315,14 +315,14 @@ codec_write(ice1712 *ice, uint8 reg_addr, uint8 data)
break;
case ICE1712_SUBDEVICE_DELTA1010:
case ICE1712_SUBDEVICE_DELTA1010LT:
ak45xx_write_gpio(ice, reg_addr, data, DELTA1010LT_CODEC_CS_0,
DELTA1010LT_CS_NONE);
ak45xx_write_gpio(ice, reg_addr, data, DELTA1010LT_CODEC_CS_1,
DELTA1010LT_CS_NONE);
ak45xx_write_gpio(ice, reg_addr, data, DELTA1010LT_CODEC_CS_2,
DELTA1010LT_CS_NONE);
ak45xx_write_gpio(ice, reg_addr, data, DELTA1010LT_CODEC_CS_3,
DELTA1010LT_CS_NONE);
ak45xx_write_gpio(ice, reg_addr, data,
DELTA1010LT_CODEC_CS_0, DELTA1010LT_CS_NONE);
ak45xx_write_gpio(ice, reg_addr, data,
DELTA1010LT_CODEC_CS_1, DELTA1010LT_CS_NONE);
ak45xx_write_gpio(ice, reg_addr, data,
DELTA1010LT_CODEC_CS_2, DELTA1010LT_CS_NONE);
ak45xx_write_gpio(ice, reg_addr, data,
DELTA1010LT_CODEC_CS_3, DELTA1010LT_CS_NONE);
break;
case ICE1712_SUBDEVICE_VX442:
ak45xx_write_gpio(ice, reg_addr, data, VX442_CODEC_CS_0, 0);
@@ -335,7 +335,7 @@ codec_write(ice1712 *ice, uint8 reg_addr, uint8 data)
void
spdif_write(ice1712 *ice, uint8 reg_addr, uint8 data)
{
switch (ice->product) {
switch (ice->config.product) {
case ICE1712_SUBDEVICE_DELTA1010:
break;
case ICE1712_SUBDEVICE_DELTADIO2496:
@@ -351,7 +351,7 @@ spdif_write(ice1712 *ice, uint8 reg_addr, uint8 data)
break;
case ICE1712_SUBDEVICE_DELTA1010LT:
cs84xx_write_gpio(ice, reg_addr, data, DELTA1010LT_SPDIF_CS,
DELTA1010LT_CS_NONE);
DELTA1010LT_CS_NONE);
break;
case ICE1712_SUBDEVICE_VX442:
cs84xx_write_gpio(ice, reg_addr, data, VX442_SPDIF_CS, 0);
@@ -364,7 +364,7 @@ uint8
codec_read(ice1712 *ice, uint8 reg_addr)
{
uint8 val = 0xFF;
switch (ice->product) {
switch (ice->config.product) {
case ICE1712_SUBDEVICE_DELTA66:
case ICE1712_SUBDEVICE_DELTA44:
val = ak45xx_read_gpio(ice, reg_addr, DELTA66_CODEC_CS_0, 0);
@@ -377,7 +377,7 @@ codec_read(ice1712 *ice, uint8 reg_addr)
case ICE1712_SUBDEVICE_DELTA1010:
case ICE1712_SUBDEVICE_DELTA1010LT:
val = ak45xx_read_gpio(ice, reg_addr, DELTA1010LT_CODEC_CS_0,
DELTA1010LT_CS_NONE);
DELTA1010LT_CS_NONE);
break;
case ICE1712_SUBDEVICE_VX442:
val = ak45xx_read_gpio(ice, reg_addr, VX442_CODEC_CS_0, 0);
@@ -392,7 +392,7 @@ uint8
spdif_read(ice1712 *ice, uint8 reg_addr)
{
uint8 val = 0xFF;
switch (ice->product) {
switch (ice->config.product) {
case ICE1712_SUBDEVICE_DELTA1010:
break;
case ICE1712_SUBDEVICE_DELTADIO2496:
@@ -408,7 +408,7 @@ spdif_read(ice1712 *ice, uint8 reg_addr)
break;
case ICE1712_SUBDEVICE_DELTA1010LT:
val = cs84xx_read_gpio(ice, reg_addr, DELTA1010LT_SPDIF_CS,
DELTA1010LT_CS_NONE);
DELTA1010LT_CS_NONE);
break;
case ICE1712_SUBDEVICE_VX442:
val = cs84xx_read_gpio(ice, reg_addr, VX442_SPDIF_CS, 0);
@@ -418,6 +418,7 @@ spdif_read(ice1712 *ice, uint8 reg_addr)
return val;
}
void
write_gpio_byte(ice1712 *ice, uint8 data, uint8 gpio_data)
{
@@ -441,6 +442,7 @@ write_gpio_byte(ice1712 *ice, uint8 data, uint8 gpio_data)
}
}
uint8
read_gpio_byte(ice1712 *ice, uint8 gpio_data)
{
@@ -453,7 +455,7 @@ read_gpio_byte(ice1712 *ice, uint8 gpio_data)
write_gpio(ice, gpio_data);
snooze(GPIO_I2C_DELAY);
if (read_gpio(ice) & ice->CommLines.data_in)
if (read_gpio(ice) &ice->CommLines.data_in)
data |= 1 << i;
gpio_data |= ice->CommLines.clock;
@@ -465,6 +467,7 @@ read_gpio_byte(ice1712 *ice, uint8 gpio_data)
return data;
}
void
ak45xx_write_gpio(ice1712 *ice, uint8 reg_addr, uint8 data,
uint8 chip_select, uint8 invert_cs)
@@ -497,6 +500,7 @@ ak45xx_write_gpio(ice1712 *ice, uint8 reg_addr, uint8 data,
snooze(GPIO_I2C_DELAY);
}
void
cs84xx_write_gpio(ice1712 *ice, uint8 reg_addr, uint8 data,
uint8 chip_select, uint8 invert_cs)
@@ -529,6 +533,7 @@ cs84xx_write_gpio(ice1712 *ice, uint8 reg_addr, uint8 data,
snooze(GPIO_I2C_DELAY);
}
uint8
cs84xx_read_gpio(ice1712 *ice, uint8 reg_addr, uint8 chip_select,
uint8 invert_cs)
@@ -586,16 +591,21 @@ cs84xx_read_gpio(ice1712 *ice, uint8 reg_addr, uint8 chip_select,
}
/*
* return -1 if error else return an uint8
*/
uint8
read_gpio(ice1712 *ice)
{//return -1 if error else return an uint8
{
return read_cci_uint8(ice, CCI_GPIO_DATA);
}
/*
* return -1 if error else return 0
*/
void
write_gpio(ice1712 *ice, uint8 value)
{//return -1 if error else return 0
{
write_cci_uint8(ice, CCI_GPIO_DATA, value);
}
src/add-ons/kernel/drivers/audio/ice1712/io.h
+43 -52
View File
@@ -1,14 +1,14 @@
/*
* ice1712 BeOS/Haiku Driver for VIA - VT1712 Multi Channel Audio Controller
* Copyright 2004-2015 Haiku, Inc. All rights reserved.
* Distributed under the terms of the MIT License.
*
* Copyright (c) 2002, Jerome Duval ([email protected])
* Copyright (c) 2003, Marcus Overhagen ([email protected])
* Copyright (c) 2007, Jerome Leveque ([email protected])
*
* All rights reserved
* Distributed under the terms of the MIT license.
* Authors:
* Jérôme Duval, [email protected]
* Marcus Overhagen, [email protected]
* Jérôme Lévêque, [email protected]
*/
#ifndef _IO_H_
#define _IO_H_
@@ -16,40 +16,34 @@
#include <SupportDefs.h>
//------------------------------------------------------
//------------------------------------------------------
//Address are [PCI_10] + xx
uint8 read_ccs_uint8(ice1712 *ice, int8 regno);
uint16 read_ccs_uint16(ice1712 *ice, int8 regno);
uint32 read_ccs_uint32(ice1712 *ice, int8 regno);
uint8 read_ccs_uint8(ice1712 *ice, int8 regno);
uint16 read_ccs_uint16(ice1712 *ice, int8 regno);
uint32 read_ccs_uint32(ice1712 *ice, int8 regno);
void write_ccs_uint8(ice1712 *ice, int8 regno, uint8 value);
void write_ccs_uint16(ice1712 *ice, int8 regno, uint16 value);
void write_ccs_uint32(ice1712 *ice, int8 regno, uint32 value);
uint8 read_cci_uint8(ice1712 *ice, int8 index);
void write_cci_uint8(ice1712 *ice, int8 index, uint8 value);
void write_ccs_uint8(ice1712 *ice, int8 regno, uint8 value);
void write_ccs_uint16(ice1712 *ice, int8 regno, uint16 value);
void write_ccs_uint32(ice1712 *ice, int8 regno, uint32 value);
//------------------------------------------------------
//------------------------------------------------------
uint8 read_cci_uint8(ice1712 *ice, int8 index);
void write_cci_uint8(ice1712 *ice, int8 index, uint8 value);
//------------------------------------------------------
//------------------------------------------------------
//Address are [PCI_14] + xx
uint8 read_ddma_uint8(ice1712 *ice, int8 regno);
uint16 read_ddma_uint16(ice1712 *ice, int8 regno);
uint32 read_ddma_uint32(ice1712 *ice, int8 regno);
uint8 read_ddma_uint8(ice1712 *ice, int8 regno);
uint16 read_ddma_uint16(ice1712 *ice, int8 regno);
uint32 read_ddma_uint32(ice1712 *ice, int8 regno);
void write_ddma_uint8(ice1712 *ice, int8 regno, uint8 value);
void write_ddma_uint16(ice1712 *ice, int8 regno, uint16 value);
void write_ddma_uint32(ice1712 *ice, int8 regno, uint32 value);
void write_ddma_uint8(ice1712 *ice, int8 regno, uint8 value);
void write_ddma_uint16(ice1712 *ice, int8 regno, uint16 value);
void write_ddma_uint32(ice1712 *ice, int8 regno, uint32 value);
//------------------------------------------------------
//------------------------------------------------------
//Address are [PCI_18] + x
uint8 read_ds_uint8(ice1712 *ice, int8 regno);
uint16 read_ds_uint16(ice1712 *ice, int8 regno);
uint32 read_ds_uint32(ice1712 *ice, int8 regno);
uint8 read_ds_uint8(ice1712 *ice, int8 regno);
uint16 read_ds_uint16(ice1712 *ice, int8 regno);
uint32 read_ds_uint32(ice1712 *ice, int8 regno);
void write_ds_uint8(ice1712 *ice, int8 regno, uint8 value);
void write_ds_uint16(ice1712 *ice, int8 regno, uint16 value);
void write_ds_uint32(ice1712 *ice, int8 regno, uint32 value);
void write_ds_uint8(ice1712 *ice, int8 regno, uint8 value);
void write_ds_uint16(ice1712 *ice, int8 regno, uint16 value);
void write_ds_uint32(ice1712 *ice, int8 regno, uint32 value);
typedef enum {
DS8_REGISTER_BUFFER_0_BASE_ADDRESS = 0,
@@ -61,26 +55,23 @@ typedef enum {
DS8_REGISTER_LEFT_RIGHT_VOLUME,
} ds8_register;
uint32 read_ds_channel_data(ice1712 *ice, uint8 channel, ds8_register index);
void write_ds_channel_data(ice1712 *ice, uint8 channel,
ds8_register index, uint32 data);
//------------------------------------------------------
//------------------------------------------------------
uint32 read_ds_channel_data(ice1712 *ice, uint8 channel, ds8_register index);
void write_ds_channel_data(ice1712 *ice, uint8 channel, ds8_register index,
uint32 data);
//Address are [PCI_1C] + xx
uint8 read_mt_uint8(ice1712 *ice, int8 regno);
uint16 read_mt_uint16(ice1712 *ice, int8 regno);
uint32 read_mt_uint32(ice1712 *ice, int8 regno);
uint8 read_mt_uint8(ice1712 *ice, int8 regno);
uint16 read_mt_uint16(ice1712 *ice, int8 regno);
uint32 read_mt_uint32(ice1712 *ice, int8 regno);
void write_mt_uint8(ice1712 *ice, int8 regno, uint8 value);
void write_mt_uint16(ice1712 *ice, int8 regno, uint16 value);
void write_mt_uint32(ice1712 *ice, int8 regno, uint32 value);
//------------------------------------------------------
//------------------------------------------------------
void write_mt_uint8(ice1712 *ice, int8 regno, uint8 value);
void write_mt_uint16(ice1712 *ice, int8 regno, uint16 value);
void write_mt_uint32(ice1712 *ice, int8 regno, uint32 value);
int16 read_i2c(ice1712 *ice, uint8 dev_addr, uint8 byte_addr);
int16 read_i2c(ice1712 *ice, uint8 dev_addr, uint8 byte_addr);
//return -1 if error else return an uint8
int16 write_i2c(ice1712 *ice, uint8 dev_addr, uint8 byte_addr, uint8 value);
int16 write_i2c(ice1712 *ice, uint8 dev_addr, uint8 byte_addr, uint8 value);
//return -1 if error else return 0
//------------------------------------------------------
@@ -101,9 +92,9 @@ uint8 spdif_read_mult(ice1712 *ice, uint8 reg_addr, uint8 datas[], uint8 size);
//------------------------------------------------------
uint8 read_gpio(ice1712 *ice);
uint8 read_gpio(ice1712 *ice);
//return -1 if error else return an uint8
void write_gpio(ice1712 *ice, uint8 value);
void write_gpio(ice1712 *ice, uint8 value);
#endif
src/add-ons/kernel/drivers/audio/ice1712/midi.c
-148
View File
@@ -1,148 +0,0 @@
/*
* ice1712 BeOS/Haiku Driver for VIA - VT1712 Multi Channel Audio Controller
*
* Copyright (c) 2002, Jerome Duval ([email protected])
* Copyright (c) 2003, Marcus Overhagen ([email protected])
* Copyright (c) 2007, Jerome Leveque ([email protected])
*
* All rights reserved
* Distributed under the terms of the MIT license.
*/
#include <midi_driver.h>
#include <string.h>
#include <stdlib.h>
#include <signal.h>
#include "ice1712.h"
#include "ice1712_reg.h"
#include "io.h"
#include "util.h"
#include "debug.h"
extern generic_mpu401_module * mpu401;
void
ice_1712_midi_interrupt_op(int32 op, void *data)
{
cpu_status status;
uint8 int_status = 0;
midi_dev *midi = (midi_dev *)data;
if (op == B_MPU_401_ENABLE_CARD_INT) {
status = lock();
int_status = read_ccs_uint8(midi->card, CCS_INTERRUPT_MASK);
int_status &= ~(midi->int_mask);
write_ccs_uint8(midi->card, CCS_INTERRUPT_MASK, int_status);
TRACE("B_MPU_401_ENABLE_CARD_INT: %s\n", midi->name);
unlock(status);
} else if (op == B_MPU_401_DISABLE_CARD_INT) {
status = lock();
int_status = read_ccs_uint8(midi->card, CCS_INTERRUPT_MASK);
int_status |= midi->int_mask;
write_ccs_uint8(midi->card, CCS_INTERRUPT_MASK, int_status);
TRACE("B_MPU_401_DISABLE_CARD_INT: %s\n", midi->name);
unlock(status);
}
TRACE("New mask status 0x%x\n", int_status);
}
status_t
ice_1712_midi_open(const char *name, uint32 flags, void **cookie)
{
int midi, card;
status_t ret = ENODEV;
TRACE("**midi_open()\n");
*cookie = NULL;
for (card = 0; card < num_cards; card++) {
for (midi = 0; midi < cards[card].config.nb_MPU401; midi++) {
if (!strcmp(name, cards[card].midi_interf[midi].name)) {
midi_dev *dev = &(cards[card].midi_interf[midi]);
ret = (*mpu401->open_hook)(dev->mpu401device, flags, cookie);
if (ret >= B_OK) {
*cookie = dev->mpu401device;
}
break;
}
}
}
return ret;
}
status_t
ice_1712_midi_close(void* cookie)
{
TRACE("**midi_close()\n");
return (*mpu401->close_hook)(cookie);
}
status_t
ice_1712_midi_free(void* cookie)
{
int midi, card;
status_t ret;
TRACE("**midi_free()\n");
ret = (*mpu401->free_hook)(cookie);
for (card = 0; card < num_cards; card++) {
for (midi = 0; midi < cards[card].config.nb_MPU401; midi++) {
if (cookie == cards[card].midi_interf[midi].mpu401device) {
cards[card].midi_interf[midi].mpu401device = NULL;
TRACE("Cleared %p card %d, midi %d\n", cookie, card, midi);
break;
}
}
}
return ret;
}
status_t
ice_1712_midi_control(void* cookie,
uint32 iop, void* data, size_t len)
{
TRACE("**midi_control()\n");
return (*mpu401->control_hook)(cookie, iop, data, len);
}
status_t
ice_1712_midi_read(void * cookie, off_t pos, void * ptr, size_t * nread)
{
status_t ret = B_ERROR;
ret = (*mpu401->read_hook)(cookie, pos, ptr, nread);
//TRACE("**midi_read(%ld)\n", ret);
return ret;
}
status_t
ice_1712_midi_write(void * cookie, off_t pos, const void * ptr,
size_t * nwritten)
{
status_t ret = B_ERROR;
ret = (*mpu401->write_hook)(cookie, pos, ptr, nwritten);
//TRACE("**midi_write(%ld)\n", ret);
return ret;
}
src/add-ons/kernel/drivers/audio/ice1712/midi.cpp
+167
View File
@@ -0,0 +1,167 @@
/*
* Copyright 2004-2015 Haiku, Inc. All rights reserved.
* Distributed under the terms of the MIT License.
*
* Authors:
* Jérôme Duval, [email protected]
* Marcus Overhagen, [email protected]
* Jérôme Lévêque, [email protected]
*/
#include <midi_driver.h>
#include <string.h>
#include <stdlib.h>
#include <signal.h>
#include "ice1712.h"
#include "ice1712_reg.h"
#include "io.h"
#include "util.h"
#include "debug.h"
extern generic_mpu401_module * mpu401;
extern int32 num_cards;
extern ice1712 cards[NUM_CARDS];
void ice1712Midi_interrupt(int32 op, void *data);
void
ice1712Midi_interrupt(int32 op, void *data)
{
cpu_status status;
uint8 int_status = 0;
ice1712Midi *midi = (ice1712Midi*)data;
if (op == B_MPU_401_ENABLE_CARD_INT) {
status = lock();
int_status = read_ccs_uint8(midi->card, CCS_INTERRUPT_MASK);
int_status &= ~(midi->int_mask);
write_ccs_uint8(midi->card, CCS_INTERRUPT_MASK, int_status);
ITRACE("B_MPU_401_ENABLE_CARD_INT: %s\n", midi->name);
unlock(status);
} else if (op == B_MPU_401_DISABLE_CARD_INT) {
status = lock();
int_status = read_ccs_uint8(midi->card, CCS_INTERRUPT_MASK);
int_status |= midi->int_mask;
write_ccs_uint8(midi->card, CCS_INTERRUPT_MASK, int_status);
ITRACE("B_MPU_401_DISABLE_CARD_INT: %s\n", midi->name);
unlock(status);
}
ITRACE("New mask status 0x%x\n", int_status);
}
static status_t
ice1712Midi_open(const char *name, uint32 flags, void **cookie)
{
int midi, card;
status_t ret = ENODEV;
ITRACE("**midi_open()\n");
*cookie = NULL;
for (card = 0; card < num_cards; card++) {
for (midi = 0; midi < cards[card].config.nb_MPU401; midi++) {
if (!strcmp(name, cards[card].midiItf[midi].name)) {
ice1712Midi *dev = &(cards[card].midiItf[midi]);
ret = (*mpu401->open_hook)(dev->mpu401device, flags, cookie);
if (ret >= B_OK) {
*cookie = dev->mpu401device;
}
break;
}
}
}
return ret;
}
static status_t
ice1712Midi_close(void* cookie)
{
ITRACE("**midi_close()\n");
return (*mpu401->close_hook)(cookie);
}
static status_t
ice1712Midi_free(void* cookie)
{
int midi, card;
status_t ret;
ITRACE("**midi_free()\n");
ret = (*mpu401->free_hook)(cookie);
for (card = 0; card < num_cards; card++) {
for (midi = 0; midi < cards[card].config.nb_MPU401; midi++) {
if (cookie == cards[card].midiItf[midi].mpu401device) {
cards[card].midiItf[midi].mpu401device = NULL;
ITRACE("Cleared %p card %d, midi %d\n", cookie, card, midi);
break;
}
}
}
return ret;
}
static status_t
ice1712Midi_control(void* cookie,
uint32 iop, void* data, size_t len)
{
ITRACE("**midi_control()\n");
return (*mpu401->control_hook)(cookie, iop, data, len);
}
static status_t
ice1712Midi_read(void * cookie, off_t pos, void * ptr, size_t * nread)
{
status_t ret = B_ERROR;
ret = (*mpu401->read_hook)(cookie, pos, ptr, nread);
ITRACE_VV("**midi_read: %" B_PRIi32 "\n", ret);
return ret;
}
static status_t
ice1712Midi_write(void * cookie, off_t pos, const void * ptr,
size_t * nwritten)
{
status_t ret = B_ERROR;
ret = (*mpu401->write_hook)(cookie, pos, ptr, nwritten);
ITRACE_VV("**midi_write: %" B_PRIi32 "\n", ret);
return ret;
}
device_hooks ice1712Midi_hooks =
{
ice1712Midi_open,
ice1712Midi_close,
ice1712Midi_free,
ice1712Midi_control,
ice1712Midi_read,
ice1712Midi_write,
NULL,
NULL,
NULL,
NULL
};
src/add-ons/kernel/drivers/audio/ice1712/multi.c → src/add-ons/kernel/drivers/audio/ice1712/multi.cpp
+502 -472
View File
File diff suppressed because it is too large Load Diff
src/add-ons/kernel/drivers/audio/ice1712/multi.h
+27 -30
View File
@@ -1,14 +1,14 @@
/*
* ice1712 BeOS/Haiku Driver for VIA - VT1712 Multi Channel Audio Controller
* Copyright 2004-2015 Haiku, Inc. All rights reserved.
* Distributed under the terms of the MIT License.
*
* Copyright (c) 2002, Jerome Duval ([email protected])
* Copyright (c) 2003, Marcus Overhagen ([email protected])
* Copyright (c) 2007, Jerome Leveque ([email protected])
*
* All rights reserved
* Distributed under the terms of the MIT license.
* Authors:
* Jérôme Duval, [email protected]
* Marcus Overhagen, [email protected]
* Jérôme Lévêque, [email protected]
*/
#ifndef _ICE1712_MULTI_H_
#define _ICE1712_MULTI_H_
@@ -30,14 +30,14 @@
#define ICE1712_MULTI_CONTROL_CHANNEL_MASK (0x0FF00000)
#define ICE1712_MULTI_CONTROL_INDEX_MASK (0x00000FFF)
#define ICE1712_MULTI_SET_CHANNEL(_c_) ((_c_ << 20) & \
#define ICE1712_MULTI_SET_CHANNEL(_c_) ((_c_ << 20) & \
ICE1712_MULTI_CONTROL_CHANNEL_MASK)
#define ICE1712_MULTI_GET_CHANNEL(_c_) ((_c_ & \
#define ICE1712_MULTI_GET_CHANNEL(_c_) ((_c_ & \
ICE1712_MULTI_CONTROL_CHANNEL_MASK) >> 20)
#define ICE1712_MULTI_SET_INDEX(_i_) (_i_ & \
#define ICE1712_MULTI_SET_INDEX(_i_) (_i_ & \
ICE1712_MULTI_CONTROL_INDEX_MASK)
#define ICE1712_MULTI_GET_INDEX(_i_) (_i_ & \
#define ICE1712_MULTI_GET_INDEX(_i_) (_i_ & \
ICE1712_MULTI_CONTROL_INDEX_MASK)
/*
@@ -51,25 +51,22 @@
#define CONTROL_IS_MASTER (0)
status_t ice1712_get_description(ice1712 *card, multi_description *data);
status_t ice1712_get_enabled_channels(ice1712 *card,
multi_channel_enable *data);
status_t ice1712_set_enabled_channels(ice1712 *card,
multi_channel_enable *data);
status_t ice1712_get_global_format(ice1712 *card, multi_format_info *data);
status_t ice1712_set_global_format(ice1712 *card, multi_format_info *data);
status_t ice1712_get_mix(ice1712 *card, multi_mix_value_info *data);
status_t ice1712_set_mix(ice1712 *card, multi_mix_value_info *data);
status_t ice1712_list_mix_channels(ice1712 *card,
multi_mix_channel_info *data);
status_t ice1712_list_mix_controls(ice1712 *card,
multi_mix_control_info *data);
status_t ice1712_list_mix_connections(ice1712 *card,
multi_mix_connection_info *data);
status_t ice1712_get_buffers(ice1712 *card, multi_buffer_list *data);
status_t ice1712_buffer_exchange(ice1712 *card, multi_buffer_info *data);
status_t ice1712_buffer_force_stop(ice1712 *card);
status_t ice1712Get_Description(ice1712 *card, multi_description *data);
status_t ice1712Get_Channel(ice1712 *card, multi_channel_enable *data);
status_t ice1712Set_Channel(ice1712 *card, multi_channel_enable *data);
status_t ice1712Get_Format(ice1712 *card, multi_format_info *data);
status_t ice1712Set_Format(ice1712 *card, multi_format_info *data);
status_t ice1712Get_MixValue(ice1712 *card, multi_mix_value_info *data);
status_t ice1712Set_MixValue(ice1712 *card, multi_mix_value_info *data);
status_t ice1712Get_MixValueChannel(ice1712 *card,
multi_mix_channel_info *data);
status_t ice1712Get_MixValueControls(ice1712 *card,
multi_mix_control_info *data);
status_t ice1712Get_MixValueConnections(ice1712 *card,
multi_mix_connection_info *data);
status_t ice1712Buffer_Get(ice1712 *card, multi_buffer_list *data);
status_t ice1712Buffer_Exchange(ice1712 *card, multi_buffer_info *data);
status_t ice1712Buffer_Stop(ice1712 *card);
#endif //_ICE1712_MULTI_H_
src/add-ons/kernel/drivers/audio/ice1712/util.c
-83
View File
@@ -1,83 +0,0 @@
/*
* ice1712 BeOS/Haiku Driver for VIA - VT1712 Multi Channel Audio Controller
*
* Copyright (c) 2002, Jerome Duval ([email protected])
* Copyright (c) 2003, Marcus Overhagen ([email protected])
* Copyright (c) 2007, Jerome Leveque ([email protected])
*
* All rights reserved
* Distributed under the terms of the MIT license.
*/
#include <Errors.h>
#include <OS.h>
#include <string.h>
#include "debug.h"
#include "util.h"
spinlock slock = B_SPINLOCK_INITIALIZER;
uint32 round_to_pagesize(uint32 size);
cpu_status
lock(void)
{
cpu_status status = disable_interrupts();
acquire_spinlock(&slock);
return status;
}
void
unlock(cpu_status status)
{
release_spinlock(&slock);
restore_interrupts(status);
}
uint32
round_to_pagesize(uint32 size)
{
return (size + B_PAGE_SIZE - 1) & ~(B_PAGE_SIZE - 1);
}
area_id
alloc_mem(void **phy, void **log, size_t size, const char *name)
{
// TODO: phy should be phys_addr_t*!
physical_entry pe;
void * logadr;
area_id areaid;
status_t rv;
TRACE("allocating %#08X bytes for %s\n", (int)size, name);
size = round_to_pagesize(size);
areaid = create_area(name, &logadr, B_ANY_KERNEL_ADDRESS, size,
B_32_BIT_CONTIGUOUS, B_READ_AREA | B_WRITE_AREA);
// TODO: The rest of the code doesn't deal correctly with physical
// addresses > 4 GB, so we have to force 32 bit addresses here.
if (areaid < B_OK) {
TRACE("couldn't allocate area %s\n",name);
return B_ERROR;
}
rv = get_memory_map(logadr,size,&pe,1);
if (rv < B_OK) {
delete_area(areaid);
TRACE("couldn't map %s\n",name);
return B_ERROR;
}
memset(logadr,0,size);
if (log)
*log = logadr;
if (phy)
*phy = (void*)(addr_t)pe.address;
TRACE("area = %d, size = %#08X, log = %#08X, phy = %#08X\n",
(int)areaid, (int)size, (int)logadr, (int)pe.address);
return areaid;
}
src/add-ons/kernel/drivers/audio/ice1712/util.cpp
+79
View File
@@ -0,0 +1,79 @@
/*
* Copyright 2004-2015 Haiku, Inc. All rights reserved.
* Distributed under the terms of the MIT License.
*
* Authors:
* Jérôme Duval, [email protected]
* Marcus Overhagen, [email protected]
* Jérôme Lévêque, [email protected]
*/
#include <Errors.h>
#include <OS.h>
#include <string.h>
#include "debug.h"
#include "util.h"
static spinlock slock = B_SPINLOCK_INITIALIZER;
static uint32 round_to_pagesize(uint32 size);
cpu_status
lock(void)
{
cpu_status status = disable_interrupts();
acquire_spinlock(&slock);
return status;
}
void
unlock(cpu_status status)
{
release_spinlock(&slock);
restore_interrupts(status);
}
uint32
round_to_pagesize(uint32 size)
{
return (size + B_PAGE_SIZE - 1) & ~(B_PAGE_SIZE - 1);
}
area_id
alloc_mem(physical_entry *phy, addr_t *log, size_t size, const char *name)
{
void * logadr;
area_id areaid;
status_t rv;
ITRACE("Allocating %s: ", name);
size = round_to_pagesize(size);
areaid = create_area(name, &logadr, B_ANY_KERNEL_ADDRESS, size,
B_32_BIT_CONTIGUOUS, B_READ_AREA | B_WRITE_AREA);
// TODO: The rest of the code doesn't deal correctly with physical
// addresses > 4 GB, so we have to force 32 bit addresses here.
if (areaid < B_OK) {
ITRACE("couldn't allocate\n");
return B_ERROR;
}
rv = get_memory_map(logadr, size, phy, 1);
if (rv < B_OK) {
delete_area(areaid);
ITRACE("couldn't map\n");
return B_ERROR;
}
if (log)
*log = (addr_t)logadr;
ITRACE("area = %" B_PRId32 ", size = %" B_PRIuSIZE ", log = 0x%" \
B_PRIXADDR ", phy = 0x%" B_PRIXPHYSADDR "\n", areaid, size,
*log, phy->address);
return areaid;
}
src/add-ons/kernel/drivers/audio/ice1712/util.h
+9 -11
View File
@@ -1,21 +1,19 @@
/*
* ice1712 BeOS/Haiku Driver for VIA - VT1712 Multi Channel Audio Controller
* Copyright 2004-2015 Haiku, Inc. All rights reserved.
* Distributed under the terms of the MIT License.
*
* Copyright (c) 2002, Jerome Duval ([email protected])
* Copyright (c) 2003, Marcus Overhagen ([email protected])
* Copyright (c) 2007, Jerome Leveque ([email protected])
*
* All rights reserved
* Distributed under the terms of the MIT license.
* Authors:
* Jérôme Duval, [email protected]
* Marcus Overhagen, [email protected]
* Jérôme Lévêque, [email protected]
*/
#ifndef _UTIL_H_
#define _UTIL_H_
#include <KernelExport.h>
area_id alloc_mem(void **phy, void **log, size_t size, const char *name);
area_id alloc_mem(physical_entry *phy, addr_t *log, size_t size,
const char *name);
cpu_status lock(void);
void unlock(cpu_status status);