the previous commit shifted the PLLsel problem from digitally connected screens to analog connected screens apparantly. That is now fixed and both should work OK. Bumped version to 1.01. +alphabranch.
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@32958 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
@@ -651,6 +651,7 @@
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#define NVDAC_PLLSEL 0x0068050c
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#define NVDAC_PLLSEL 0x0068050c
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#define NVDAC_OUTPUT 0x0068052c
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#define NVDAC_OUTPUT 0x0068052c
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#define NVDAC_PIXPLLC2 0x00680578
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#define NVDAC_PIXPLLC2 0x00680578
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#define NVDAC_NV40_PLLSEL2 0x00680580
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#define NVDAC_GENCTRL 0x00680600
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#define NVDAC_GENCTRL 0x00680600
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#define NVDAC_TSTCTRL 0x00680608
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#define NVDAC_TSTCTRL 0x00680608
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#define NVDAC_TSTDATA 0x00680610
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#define NVDAC_TSTDATA 0x00680610
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@@ -206,10 +206,12 @@ status_t nv_dac_set_pix_pll(display_mode target)
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/* note:
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/* note:
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* setup PLL assignment _after_ programming PLL */
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* setup PLL assignment _after_ programming PLL */
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if (si->ps.secondary_head) {
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if (si->ps.secondary_head) {
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if (si->ps.card_arch < NV40A)
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if (si->ps.card_arch < NV40A) {
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DACW(PLLSEL, 0x30000f00);
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DACW(PLLSEL, 0x30000f00);
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else
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} else {
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DACW(NV40_PLLSEL2, (DACR(NV40_PLLSEL2) & ~0x10000100));
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DACW(PLLSEL, 0x30000f04);
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DACW(PLLSEL, 0x30000f04);
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}
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} else {
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} else {
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DACW(PLLSEL, 0x10000700);
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DACW(PLLSEL, 0x10000700);
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}
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}
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@@ -208,13 +208,11 @@ status_t nv_dac2_set_pix_pll(display_mode target)
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/* (confirmed PLLSEL to be a write-only register on NV04 and NV11!) */
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/* (confirmed PLLSEL to be a write-only register on NV04 and NV11!) */
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/* note:
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/* note:
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* setup PLL assignment _after_ programming PLL */
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* setup PLL assignment _after_ programming PLL */
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if (si->ps.secondary_head) {
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if (si->ps.card_arch < NV40A) {
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if (si->ps.card_arch < NV40A)
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DACW(PLLSEL, 0x30000f00);
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DACW(PLLSEL, 0x30000f00);
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else
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DACW(PLLSEL, 0x30000f04);
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} else {
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} else {
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DACW(PLLSEL, 0x10000700);
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DACW(NV40_PLLSEL2, (DACR(NV40_PLLSEL2) & ~0x10000100));
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DACW(PLLSEL, 0x30000f04);
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}
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}
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LOG(2,("DAC2: PIX PLL frequency should be locked now...\n"));
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LOG(2,("DAC2: PIX PLL frequency should be locked now...\n"));
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@@ -92,7 +92,7 @@ status_t nv_general_powerup()
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{
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{
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status_t status;
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status_t status;
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LOG(1,("POWERUP: Haiku nVidia Accelerant 1.00 running.\n"));
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LOG(1,("POWERUP: Haiku nVidia Accelerant 1.01 running.\n"));
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/* log VBLANK INT usability status */
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/* log VBLANK INT usability status */
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if (si->ps.int_assigned)
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if (si->ps.int_assigned)
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@@ -4,7 +4,7 @@
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</head>
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</head>
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<body>
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<body>
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<p><h2>Changes done for each driverversion:</h2></p>
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<p><h2>Changes done for each driverversion:</h2></p>
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<p><h1>head (SVN 1.00, Rudolf)</h1></p>
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<p><h1>head (SVN 1.01, Rudolf)</h1></p>
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<ul>
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<ul>
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<li>Fixed driver assuming enabling AGP mode succeeded on some occasions if it did not block it itself. Blocking AGP mode completely via the AGP busmanager (option 'block_agp') resulted in a crashing acceleration engine because it was setup for AGP transfers instead of using PCI transfers. Error was solved with help from user kraton.
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<li>Fixed driver assuming enabling AGP mode succeeded on some occasions if it did not block it itself. Blocking AGP mode completely via the AGP busmanager (option 'block_agp') resulted in a crashing acceleration engine because it was setup for AGP transfers instead of using PCI transfers. Error was solved with help from user kraton.
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<li>Fixed shared_info struct problem occuring when 3D 'accelerant' is used (tested Alpha 4.1): the TVencoder type definition list apparantly gets some memory assigned these days when done inside the definition of shared_info. Moved encoder list outside the shared_info definition.
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<li>Fixed shared_info struct problem occuring when 3D 'accelerant' is used (tested Alpha 4.1): the TVencoder type definition list apparantly gets some memory assigned these days when done inside the definition of shared_info. Moved encoder list outside the shared_info definition.
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