radeon_hd: cleanup some logic; no functional change
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@@ -272,6 +272,8 @@ detect_displays()
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encoder_external_setup(id, 23860,
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encoder_external_setup(id, 23860,
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EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
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EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
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gDisplay[displayIndex]->attached = true;
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gDisplay[displayIndex]->attached = true;
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// TODO: DDC Router switching for DisplayPort (and others?)
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} else if (gConnector[id]->type == VIDEO_CONNECTOR_LVDS) {
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} else if (gConnector[id]->type == VIDEO_CONNECTOR_LVDS) {
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#endif
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#endif
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if (gConnector[id]->type == VIDEO_CONNECTOR_LVDS) {
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if (gConnector[id]->type == VIDEO_CONNECTOR_LVDS) {
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@@ -1351,9 +1351,11 @@ transmitter_dig_setup(uint32 connectorIndex, uint32 pixelClock,
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// Select the PLL for the PHY
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// Select the PLL for the PHY
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// DP PHY to be clocked from external src if possible
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// DP PHY to be clocked from external src if possible
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// DCE4 has external DCPLL clock for DP
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if (isDP && gInfo->dpExternalClock) {
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if (isDP && gInfo->dpExternalClock) {
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// use external clock source
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// use external clock source (id'ed to 2 on DCE4)
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args.v3.acConfig.ucRefClkSource = ATOM_DCPLL;
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args.v3.acConfig.ucRefClkSource = 2; // EXT clock
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} else
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} else
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args.v3.acConfig.ucRefClkSource = pll->id;
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args.v3.acConfig.ucRefClkSource = pll->id;
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@@ -1417,6 +1419,7 @@ transmitter_dig_setup(uint32 connectorIndex, uint32 pixelClock,
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// Select the PLL for the PHY
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// Select the PLL for the PHY
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// DP PHY to be clocked from external src if possible
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// DP PHY to be clocked from external src if possible
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// DCE5, DCPLL usually generates the DP ref clock
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if (isDP) {
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if (isDP) {
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if (gInfo->dpExternalClock > 0) {
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if (gInfo->dpExternalClock > 0) {
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args.v4.acConfig.ucRefClkSource
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args.v4.acConfig.ucRefClkSource
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