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intel_extreme: Some basic pipe cleanup

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This commit is contained in:
Alexander von Gluck IV
2015-11-17 20:12:41 -06:00
parent e5494f1bb2
commit 32807945aa
2 changed files with 17 additions and 19 deletions
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src/add-ons/accelerants/intel_extreme/DisplayPipe.cpp
+13 -15
View File
@@ -94,9 +94,6 @@ DisplayPipe::Enable(display_mode* target, addr_t portAddress)
return; return;
} }
// Wait for the clocks to stabilize
spin(150);
// update timing (fPipeBase bumps the DISPLAY_A to B when needed) // update timing (fPipeBase bumps the DISPLAY_A to B when needed)
write32(fPipeBase + REGISTER_REGISTER(INTEL_DISPLAY_A_HTOTAL), write32(fPipeBase + REGISTER_REGISTER(INTEL_DISPLAY_A_HTOTAL),
((uint32)(target->timing.h_total - 1) << 16) ((uint32)(target->timing.h_total - 1) << 16)
@@ -118,24 +115,24 @@ DisplayPipe::Enable(display_mode* target, addr_t portAddress)
((uint32)(target->timing.v_sync_end - 1) << 16) ((uint32)(target->timing.v_sync_end - 1) << 16)
| ((uint32)target->timing.v_sync_start - 1)); | ((uint32)target->timing.v_sync_start - 1));
// XXX: Is it ok to do these on non-digital?
write32(fPipeBase + REGISTER_REGISTER(INTEL_DISPLAY_A_POS), 0); write32(fPipeBase + REGISTER_REGISTER(INTEL_DISPLAY_A_POS), 0);
write32(fPipeBase + REGISTER_REGISTER(INTEL_DISPLAY_A_IMAGE_SIZE),
((uint32)(target->virtual_width - 1) << 16)
| ((uint32)target->virtual_height - 1));
write32(fPipeBase + REGISTER_REGISTER(INTEL_DISPLAY_A_PIPE_SIZE),
((uint32)(target->timing.v_display - 1) << 16)
| ((uint32)target->timing.h_display - 1));
// This is useful for debugging: it sets the border to red, so you // This is useful for debugging: it sets the border to red, so you
// can see what is border and what is porch (black area around the // can see what is border and what is porch (black area around the
// sync) // sync)
//write32(fPipeBase + REGISTER_REGISTER(INTEL_DISPLAY_A_RED), 0x00FF0000); //write32(fPipeBase + REGISTER_REGISTER(INTEL_DISPLAY_A_RED), 0x00FF0000);
// TODO: Review these // XXX: Is it ok to do this on non-analog?
write32(fPipeBase + REGISTER_REGISTER(INTEL_DISPLAY_A_IMAGE_SIZE), write32(portAddress, (read32(portAddress) & ~(DISPLAY_MONITOR_POLARITY_MASK
((uint32)(target->virtual_width - 1) << 16) | DISPLAY_MONITOR_VGA_POLARITY))
| ((uint32)target->virtual_height - 1));
write32(fPipeBase + REGISTER_REGISTER(INTEL_DISPLAY_A_PIPE_SIZE),
((uint32)(target->timing.v_display - 1) << 16)
| ((uint32)target->timing.h_display - 1));
write32(portAddress, (read32(portAddress)
& ~(DISPLAY_MONITOR_POLARITY_MASK
| DISPLAY_MONITOR_VGA_POLARITY))
| ((target->timing.flags & B_POSITIVE_HSYNC) != 0 | ((target->timing.flags & B_POSITIVE_HSYNC) != 0
? DISPLAY_MONITOR_POSITIVE_HSYNC : 0) ? DISPLAY_MONITOR_POSITIVE_HSYNC : 0)
| ((target->timing.flags & B_POSITIVE_VSYNC) != 0 | ((target->timing.flags & B_POSITIVE_VSYNC) != 0
@@ -235,7 +232,8 @@ DisplayPipe::ConfigureTimings(const pll_divisors& divisors, uint32 pixelClock,
pll |= DISPLAY_PLL_POST1_DIVIDE_2; pll |= DISPLAY_PLL_POST1_DIVIDE_2;
} }
write32(pllControl, pll); // Allow the PLL to warm up by masking its bit.
write32(pllControl, pll & ~DISPLAY_PLL_NO_VGA_CONTROL);
read32(pllControl); read32(pllControl);
spin(150); spin(150);
write32(pllControl, pll); write32(pllControl, pll);
src/add-ons/accelerants/intel_extreme/mode.cpp
+4 -4
View File
@@ -622,9 +622,6 @@ if (first) {
TRACE("%s: Port configuration completed successfully!\n", __func__); TRACE("%s: Port configuration completed successfully!\n", __func__);
// RIP DIGITAL / LVDS (strange..)
// RIP ANALOG
// We set the same color mode across all pipes // We set the same color mode across all pipes
program_pipe_color_modes(colorMode); program_pipe_color_modes(colorMode);
@@ -656,7 +653,10 @@ intel_get_display_mode(display_mode* _currentMode)
{ {
CALLED(); CALLED();
retrieve_current_mode(*_currentMode, INTEL_DISPLAY_A_PLL); *_currentMode = gInfo->shared_info->current_mode;
// This seems unreliable. We should always know the current_mode
//retrieve_current_mode(*_currentMode, INTEL_DISPLAY_A_PLL);
return B_OK; return B_OK;
} }