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* style cleanup of shared storage names

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* return better data on card 
* display chipset flags in screen preflet


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@43226 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Alexander von Gluck IV
2011-11-08 19:50:07 +00:00
parent 76a3e009dd
commit 359b926f79
9 changed files with 103 additions and 49 deletions
Download Patch File Download Diff File Expand all files Collapse all files
headers/private/graphics/radeon_hd/radeon_hd.h
+5 -4
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@@ -105,8 +105,8 @@ struct overlay_registers;
struct radeon_shared_info {
uint32 device_index; // accelerant index
uint32 device_id; // device pciid
uint32 deviceIndex; // accelerant index
uint32 pciID; // device pciid
area_id mode_list_area; // area containing display mode list
uint32 mode_count;
@@ -156,11 +156,12 @@ struct radeon_shared_info {
uint16 cursor_hot_x;
uint16 cursor_hot_y;
uint16 device_chipset;
char deviceName[32];
uint16 chipsetID;
char chipsetName[16];
uint32 chipsetFlags;
uint8 dceMajor;
uint8 dceMinor;
char device_identifier[32];
};
//----------------- ioctl() interface ----------------
src/add-ons/accelerants/radeon_hd/accelerant.cpp
+12 -2
View File
@@ -309,13 +309,23 @@ radeon_uninit_accelerant(void)
status_t
radeon_get_accelerant_device_info(accelerant_device_info *di)
{
radeon_shared_info &info = *gInfo->shared_info;
di->version = B_ACCELERANT_VERSION;
strcpy(di->name, gInfo->shared_info->device_identifier);
strcpy(di->name, info.deviceName);
char chipset[32];
sprintf(chipset, "r%X", gInfo->shared_info->device_chipset);
sprintf(chipset, "%s", gInfo->shared_info->chipsetName);
strcpy(di->chipset, chipset);
// add flags onto chipset name
if ((info.chipsetFlags & CHIP_IGP) != 0)
strcat(di->chipset, " IGP");
if ((info.chipsetFlags & CHIP_MOBILE) != 0)
strcat(di->chipset, " Mobile");
if ((info.chipsetFlags & CHIP_APU) != 0)
strcat(di->chipset, " APU");
strcpy(di->serial_no, "None" );
di->memory = gInfo->shared_info->graphics_memory_size;
src/add-ons/accelerants/radeon_hd/bios.cpp
+6 -6
View File
@@ -36,7 +36,7 @@ radeon_bios_init_scratch()
uint32 biosScratch2;
uint32 biosScratch6;
if (info.device_chipset >= RADEON_R600) {
if (info.chipsetID >= RADEON_R600) {
biosScratch2 = Read32(OUT, R600_BIOS_2_SCRATCH);
biosScratch6 = Read32(OUT, R600_BIOS_6_SCRATCH);
} else {
@@ -49,7 +49,7 @@ radeon_bios_init_scratch()
biosScratch6 |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
// bios shouldn't handle mode switching
if (info.device_chipset >= RADEON_R600) {
if (info.chipsetID >= RADEON_R600) {
Write32(OUT, R600_BIOS_2_SCRATCH, biosScratch2);
Write32(OUT, R600_BIOS_6_SCRATCH, biosScratch6);
} else {
@@ -67,7 +67,7 @@ radeon_bios_isposted()
radeon_shared_info &info = *gInfo->shared_info;
uint32 reg;
if (info.device_chipset == RADEON_PALM) {
if (info.chipsetID == RADEON_PALM) {
// palms
reg = Read32(OUT, EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET)
@@ -75,7 +75,7 @@ radeon_bios_isposted()
+ EVERGREEN_CRTC1_REGISTER_OFFSET);
if ((reg & EVERGREEN_CRTC_MASTER_EN) != 0)
return true;
} else if (info.device_chipset >= RADEON_CEDAR) {
} else if (info.chipsetID >= RADEON_CEDAR) {
// evergreen or higher
reg = Read32(OUT, EVERGREEN_CRTC_CONTROL
+ EVERGREEN_CRTC0_REGISTER_OFFSET)
@@ -91,7 +91,7 @@ radeon_bios_isposted()
+ EVERGREEN_CRTC5_REGISTER_OFFSET);
if ((reg & EVERGREEN_CRTC_MASTER_EN) != 0)
return true;
} else if (info.device_chipset >= RADEON_R420) {
} else if (info.chipsetID >= RADEON_R420) {
// avivio through r700
reg = Read32(OUT, AVIVO_D1CRTC_CONTROL) |
Read32(OUT, AVIVO_D2CRTC_CONTROL);
@@ -181,7 +181,7 @@ radeon_dump_bios()
FILE* fp;
char filename[255];
sprintf(filename, "/boot/common/cache/tmp/radeon_hd_bios_1002_%" B_PRIx32
"_%" B_PRIu32 ".bin", info.device_id, info.device_index);
"_%" B_PRIu32 ".bin", info.pciID, info.deviceIndex);
fp = fopen(filename, "wb");
if (fp == NULL) {
src/add-ons/accelerants/radeon_hd/display.cpp
+9 -9
View File
@@ -40,7 +40,7 @@ init_registers(register_info* regs, uint8 crtcID)
radeon_shared_info &info = *gInfo->shared_info;
if (info.device_chipset >= RADEON_CEDAR) {
if (info.chipsetID >= RADEON_CEDAR) {
// Evergreen
uint32 offset = 0;
@@ -104,7 +104,7 @@ init_registers(register_info* regs, uint8 crtcID)
regs->viewportStart = EVERGREEN_VIEWPORT_START + offset;
regs->viewportSize = EVERGREEN_VIEWPORT_SIZE + offset;
} else if (info.device_chipset >= RADEON_RV770) {
} else if (info.chipsetID >= RADEON_RV770) {
// R700 series
uint32 offset = 0;
@@ -151,7 +151,7 @@ init_registers(register_info* regs, uint8 crtcID)
regs->viewportStart = AVIVO_D1MODE_VIEWPORT_START + offset;
regs->viewportSize = AVIVO_D1MODE_VIEWPORT_SIZE + offset;
} else if (info.device_chipset >= RADEON_R600) {
} else if (info.chipsetID >= RADEON_R600) {
// R600 series+
uint32 offset = 0;
@@ -199,13 +199,13 @@ init_registers(register_info* regs, uint8 crtcID)
regs->viewportSize = AVIVO_D1MODE_VIEWPORT_SIZE + offset;
} else {
// this really shouldn't happen unless a driver PCIID chipset is wrong
TRACE("%s, unknown Radeon chipset: r%X\n", __func__,
info.device_chipset);
TRACE("%s, unknown Radeon chipset: %s\n", __func__,
info.chipsetName);
return B_ERROR;
}
TRACE("%s, registers for ATI chipset r%X crt #%d loaded\n", __func__,
info.device_chipset, crtcID);
TRACE("%s, registers for ATI chipset %s crt #%d loaded\n", __func__,
info.chipsetName, crtcID);
return B_OK;
}
@@ -960,7 +960,7 @@ display_crtc_fb_set(uint8 crtcID, display_mode *mode)
TRACE("%s: Framebuffer at: 0x%" B_PRIX64 "\n", __func__, fbAddress);
if (info.device_chipset >= RADEON_RV770) {
if (info.chipsetID >= RADEON_RV770) {
TRACE("%s: Set SurfaceAddress High: 0x%" B_PRIX32 "\n",
__func__, (fbAddress >> 32) & 0xf);
@@ -976,7 +976,7 @@ display_crtc_fb_set(uint8 crtcID, display_mode *mode)
Write32(OUT, regs->grphPrimarySurfaceAddr, (fbAddress & 0xFFFFFFFF));
Write32(OUT, regs->grphSecondarySurfaceAddr, (fbAddress & 0xFFFFFFFF));
if (info.device_chipset >= RADEON_R600) {
if (info.chipsetID >= RADEON_R600) {
Write32(CRT, regs->grphControl, fbFormat);
Write32(CRT, regs->grphSwapControl, fbSwap);
}
src/add-ons/accelerants/radeon_hd/gpu.cpp
+6 -6
View File
@@ -48,7 +48,7 @@ radeon_gpu_reset()
ERROR("%s: Timeout waiting for MC to idle!\n", __func__);
}
if (info.device_chipset < RADEON_CEDAR) {
if (info.chipsetID < RADEON_CEDAR) {
Write32(OUT, CP_ME_CNTL, CP_ME_HALT);
// Disable Command Processor parsing / prefetching
@@ -444,9 +444,9 @@ radeon_gpu_mc_init()
radeon_shared_info &info = *gInfo->shared_info;
uint32 fbVMLocationReg;
if (info.device_chipset >= RADEON_CEDAR) {
if (info.chipsetID >= RADEON_CEDAR) {
fbVMLocationReg = EVERGREEN_MC_VM_FB_LOCATION;
} else if (info.device_chipset >= RADEON_RV770) {
} else if (info.chipsetID >= RADEON_RV770) {
fbVMLocationReg = R700_MC_VM_FB_LOCATION;
} else {
fbVMLocationReg = R600_MC_VM_FB_LOCATION;
@@ -486,11 +486,11 @@ radeon_gpu_mc_setup()
TRACE("%s: vramStart: 0x%" B_PRIX64 ", vramEnd: 0x%" B_PRIX64 "\n",
__func__, gInfo->fb.vramStart, gInfo->fb.vramEnd);
if (info.device_chipset >= RADEON_CEDAR)
if (info.chipsetID >= RADEON_CEDAR)
return radeon_gpu_mc_setup_evergreen();
if (info.device_chipset >= RADEON_RV770)
if (info.chipsetID >= RADEON_RV770)
return radeon_gpu_mc_setup_r700();
else if (info.device_chipset >= RADEON_R600)
else if (info.chipsetID >= RADEON_R600)
return radeon_gpu_mc_setup_r600();
return B_ERROR;
src/add-ons/accelerants/radeon_hd/pll.cpp
+1 -1
View File
@@ -303,7 +303,7 @@ pll_setup_flags(pll_info *pll, uint8 crtcID)
pll->flags |= PLL_PREFER_LOW_REF_DIV;
if (info.device_chipset < RADEON_RV770)
if (info.chipsetID < RADEON_RV770)
pll->flags |= PLL_PREFER_MINM_OVER_MAXP;
src/add-ons/kernel/drivers/graphics/radeon_hd/driver.cpp
+8 -8
View File
@@ -39,12 +39,12 @@
// list of supported devices
const struct supported_device {
uint32 device_id;
uint32 pciID;
uint8 dceMajor; // Display block family
uint8 dceMinor; // Display block family
uint16 chipset;
uint16 chipsetID;
uint32 chipsetFlags;
const char* name;
const char* deviceName;
} kSupportedDevices[] = {
// R400 Series (Radeon) DCE 0.0 (*very* early AtomBIOS)
// R500 Series (Radeon Xxxx) DCE 1.0
@@ -233,7 +233,7 @@ get_next_radeon_hd(int32 *_cookie, pci_info &info, uint32 &type)
// check device
for (uint32 i = 0; i < sizeof(kSupportedDevices)
/ sizeof(kSupportedDevices[0]); i++) {
if (info.device_id == kSupportedDevices[i].device_id) {
if (info.device_id == kSupportedDevices[i].pciID) {
type = i;
*_cookie = index + 1;
return B_OK;
@@ -327,15 +327,15 @@ init_driver(void)
gDeviceInfo[found]->id = found;
gDeviceInfo[found]->pci = info;
gDeviceInfo[found]->registers = (uint8 *)info->u.h0.base_registers[0];
gDeviceInfo[found]->device_id = kSupportedDevices[type].device_id;
gDeviceInfo[found]->device_identifier = kSupportedDevices[type].name;
gDeviceInfo[found]->device_chipset = kSupportedDevices[type].chipset;
gDeviceInfo[found]->pciID = kSupportedDevices[type].pciID;
gDeviceInfo[found]->deviceName = kSupportedDevices[type].deviceName;
gDeviceInfo[found]->chipsetID = kSupportedDevices[type].chipsetID;
gDeviceInfo[found]->dceMajor = kSupportedDevices[type].dceMajor;
gDeviceInfo[found]->dceMinor = kSupportedDevices[type].dceMinor;
gDeviceInfo[found]->chipsetFlags = kSupportedDevices[type].chipsetFlags;
dprintf(DEVICE_NAME ": GPU(%ld) %s, revision = 0x%x\n", found,
kSupportedDevices[type].name, info->revision);
kSupportedDevices[type].deviceName, info->revision);
found++;
}
src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp
+52 -10
View File
@@ -37,6 +37,46 @@
#define ERROR(x...) dprintf("radeon_hd: " x)
static const char radeon_chip_name[][16] = {
"R420",
"RV515",
"R520",
"RV530",
"RV560",
"RV570",
"R580",
"R600",
"RV610",
"RV630",
"RV670",
"RV620",
"RV635",
"RS780",
"RS880",
"RV770",
"RV730",
"RV710",
"RV740",
"Cedar",
"Redwood",
"Juniper",
"Cypress",
"Hemlock",
"Palm",
"Sumo",
"Sumo2",
"Caicos",
"Turks",
"Barts",
"Cayman",
"Antilles",
"Lombok",
"Thames",
"Tahiti",
"New Zealand"
};
// #pragma mark -
@@ -449,8 +489,8 @@ radeon_hd_init(radeon_info &info)
TRACE("card(%ld): %s: called\n", info.id, __func__);
ERROR("%s: card(%ld): "
"Radeon r%" B_PRIX16 " 1002:%" B_PRIX32 "\n",
__func__, info.id, info.device_chipset, info.device_id);
"Radeon %s 1002:%" B_PRIX32 "\n", __func__, info.id,
radeon_chip_name[info.chipsetID], info.pciID);
// *** Map shared info
AreaKeeper sharedCreator;
@@ -481,7 +521,7 @@ radeon_hd_init(radeon_info &info)
mmioMapper.Detach();
// *** Populate frame buffer information
if (info.shared_info->device_chipset >= RADEON_CEDAR) {
if (info.shared_info->chipsetID >= RADEON_CEDAR) {
// Evergreen+ has memory stored in MB
info.shared_info->graphics_memory_size
= read32(info.registers + CONFIG_MEMSIZE) * 1024;
@@ -531,14 +571,16 @@ radeon_hd_init(radeon_info &info)
= info.pci->u.h0.base_registers[PCI_BAR_FB];
// Pass common information to accelerant
info.shared_info->device_index = info.id;
info.shared_info->device_id = info.device_id;
info.shared_info->device_chipset = info.device_chipset;
info.shared_info->deviceIndex = info.id;
info.shared_info->pciID = info.pciID;
info.shared_info->chipsetID = info.chipsetID;
info.shared_info->chipsetFlags = info.chipsetFlags;
info.shared_info->dceMajor = info.dceMajor;
info.shared_info->dceMinor = info.dceMinor;
info.shared_info->registers_area = info.registers_area;
strcpy(info.shared_info->device_identifier, info.device_identifier);
strcpy(info.shared_info->deviceName, info.deviceName);
strcpy(info.shared_info->chipsetName,
radeon_chip_name[info.chipsetID]);
// *** AtomBIOS mapping
// First we try an active bios read
@@ -546,11 +588,11 @@ radeon_hd_init(radeon_info &info)
if (biosStatus != B_OK) {
// If the active read fails, we try a disabled read
if (info.device_chipset >= RADEON_BARTS)
if (info.chipsetID >= RADEON_BARTS)
biosStatus = radeon_hd_getbios_ni(info);
else if (info.device_chipset >= RADEON_RV770)
else if (info.chipsetID >= RADEON_RV770)
biosStatus = radeon_hd_getbios_r700(info);
else if (info.device_chipset >= RADEON_R600)
else if (info.chipsetID >= RADEON_R600)
biosStatus = radeon_hd_getbios_r600(info);
// else avivo_read_disabled_bios
}
src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd_private.h
+4 -3
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@@ -45,9 +45,10 @@ struct radeon_info {
struct radeon_shared_info* shared_info;
area_id shared_area;
const char* device_identifier;
uint32 device_id;
uint16 device_chipset;
uint32 pciID;
const char* deviceName;
uint16 chipsetID;
const char* chipsetName;
uint32 chipsetFlags;
uint8 dceMajor;
uint8 dceMinor;