openBeOS_Matrox_V0.13beta1_src
git-svn-id: file:///srv/svn/repos/haiku/trunk/current@5511 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
shatty
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/*
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Copyright 1999, Be Incorporated. All Rights Reserved.
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This file may be used under the terms of the Be Sample Code License.
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Other authors:
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Mark Watson;
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Apsed;
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Rudolf Cornelissen 10/2002.
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*/
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#ifndef DRIVERINTERFACE_H
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#define DRIVERINTERFACE_H
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#include <Accelerant.h>
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#include "video_overlay.h"
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#include <Drivers.h>
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#include <PCI.h>
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#include <OS.h>
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#define DRIVER_PREFIX "mga" // apsed
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/*
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Internal driver state (also for sharing info between driver and accelerant)
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*/
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#if defined(__cplusplus)
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extern "C" {
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#endif
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typedef struct {
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sem_id sem;
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int32 ben;
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} benaphore;
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#define INIT_BEN(x) x.sem = create_sem(0, "G400 "#x" benaphore"); x.ben = 0;
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#define AQUIRE_BEN(x) if((atomic_add(&(x.ben), 1)) >= 1) acquire_sem(x.sem);
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#define RELEASE_BEN(x) if((atomic_add(&(x.ben), -1)) > 1) release_sem(x.sem);
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#define DELETE_BEN(x) delete_sem(x.sem);
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#define GX00_PRIVATE_DATA_MAGIC 0x0009 /* a private driver rev, of sorts */
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/*dualhead extensions to flags*/
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#define DUALHEAD_OFF (0<<6)
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#define DUALHEAD_CLONE (1<<6)
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#define DUALHEAD_ON (2<<6)
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#define DUALHEAD_SWITCH (3<<6)
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#define DUALHEAD_BITS (3<<6)
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#define DUALHEAD_CAPABLE (1<<8)
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#define TV_BITS (3<<9)
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#define TV_MON (0<<9
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#define TV_PAL (1<<9)
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#define TV_NTSC (2<<9)
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#define TV_CAPABLE (1<<11)
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#define SKD_MOVE_CURSOR 0x00000001
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#define SKD_PROGRAM_CLUT 0x00000002
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#define SKD_SET_START_ADDR 0x00000004
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#define SKD_SET_CURSOR 0x00000008
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#define SKD_HANDLER_INSTALLED 0x80000000
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enum {
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GX00_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1,
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GX00_GET_PCI,
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GX00_SET_PCI,
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GX00_DEVICE_NAME,
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GX00_RUN_INTERRUPTS
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};
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/* max. number of overlay buffers */
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#define MAXBUFFERS 3
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/* max. pixelclock speed the BES supports */
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#define BESMAXSPEED 135000
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/* internal used info on overlay buffers */
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typedef struct
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{
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uint16 slopspace;
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uint32 size;
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} int_buf_info;
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typedef struct settings { // apsed, see comments in mga.settings
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// for driver
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char accelerant[B_FILE_NAME_LENGTH];
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bool dumprom;
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// for accelerant
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uint32 logmask;
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uint32 memory;
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bool usebios;
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bool hardcursor;
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} settings;
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/*shared info*/
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typedef struct {
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/*a few ID things*/
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uint16 vendor_id; /* PCI vendor ID, from pci_info */
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uint16 device_id; /* PCI device ID, from pci_info */
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uint8 revision; /* PCI device revsion, from pci_info */
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/* bug workaround for 4.5.0 */
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uint32 use_clone_bugfix; /*for 4.5.0, cloning of physical memory does not work*/
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uint32 * clone_bugfix_regs;
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/*memory mappings*/
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area_id regs_area; /* Kernel's area_id for the memory mapped registers.
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It will be cloned into the accelerant's address
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space. */
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area_id fb_area; /* Frame buffer's area_id. The addresses are shared with all teams. */
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area_id pseudo_dma_area; /* Pseudo dma area_id. Shared by all teams. */
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area_id dma_buffer_area; /* Area assigned for dma*/
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void *framebuffer; /* As viewed from virtual memory */
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void *framebuffer_pci; /* As viewed from the PCI bus (for DMA) */
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void *pseudo_dma; /* As viewed from virtual memory */
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void *dma_buffer; /* buffer for dma*/
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void *dma_buffer_pci; /* buffer for dma - from PCI bus*/
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/*screenmode list*/
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area_id mode_area; /* Contains the list of display modes the driver supports */
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uint32 mode_count; /* Number of display modes in the list */
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/*flags - used by driver*/
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uint32 flags;
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/*vblank semaphore*/
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sem_id vblank; /* The vertical blank semaphore. Ownership will be
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transfered to the team opening the device first */
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/*cursor information*/
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struct {
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uint16 hot_x; /* Cursor hot spot. The top left corner of the cursor */
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uint16 hot_y; /* is 0,0 */
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uint16 x; /* The location of the cursor hot spot on the */
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uint16 y; /* desktop */
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uint16 width; /* Width and height of the cursor shape (always 16!) */
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uint16 height;
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bool is_visible; /* Is the cursor currently displayed? */
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}cursor;
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/*colour lookup table*/
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uint8 color_data[3 * 256]; /* Colour lookup table - as used by DAC */
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/*more display mode stuff*/
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display_mode dm; /* current display mode configuration */
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/*frame buffer config - for BDirectScreen*/
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frame_buffer_config fbc; /* bytes_per_row and start of frame buffer */
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/*acceleration engine*/
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struct {
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uint32 count; /* last dwgsync slot used */
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uint32 last_idle; /* last dwgsync slot we *know* the engine was idle after */
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benaphore lock; /* for serializing access to the acceleration engine */
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} engine;
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/* card info - information gathered from PINS (and other sources) */
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enum
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{ // card_type in order of date of MGA chip design
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MILL=0,
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MYST,
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MIL2,
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G100,
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G200,
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G400,
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G400MAX,
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G450,
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G550
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};
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struct
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{
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/*specialised registers for initialisation*/
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//will be deleted, will be replaced by new Pins implementation:
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//these are nolonger used by G100.
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uint32 mem_ctl;
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uint32 mem_type;
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uint8 membuf; /*memory buffer type*/
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uint32 mem_rd;
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uint32 mem_rfhcnt;
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/*temporary extra info for G450*/
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//will be deleted, will be replaced by new Pins implementation:
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uint32 option;
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uint32 option2;
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uint32 option4;
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uint32 maccess;
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/* general card information */
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uint32 card_type; /* see card_type enum above */
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status_t pins_status; /* B_OK if read correctly, B_ERROR if faked */
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bool sdram; /* TRUE if SDRAM card: needed info for 2D acceleration */
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/* newly implemented PINS: will replace most of the above.. */
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float f_ref; /* PLL reference-oscillator frequency (Mhz) */
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uint32 max_system_vco; /* graphics engine PLL VCO limits (Mhz) */
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uint32 min_system_vco;
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uint32 max_pixel_vco; /* dac1 PLL VCO limits (Mhz) */
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uint32 min_pixel_vco;
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uint32 max_video_vco; /* dac2, maven PLL VCO limits (Mhz) */
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uint32 min_video_vco;
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uint32 std_engine_clock; /* graphics engine clock speed needed (Mhz) */
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uint32 std_engine_clock_dh;
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uint32 max_dac1_clock; /* dac1 limits (Mhz) */
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uint32 max_dac1_clock_8; /* dac1 limits correlated to RAMspeed limits (Mhz) */
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uint32 max_dac1_clock_16;
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uint32 max_dac1_clock_24;
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uint32 max_dac1_clock_32;
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uint32 max_dac1_clock_32dh;
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uint32 max_dac2_clock; /* dac2 limits (Mhz) */
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uint32 max_dac2_clock_8; /* dac2, maven limits correlated to RAMspeed limits (Mhz) */
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uint32 max_dac2_clock_16;
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uint32 max_dac2_clock_24;
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uint32 max_dac2_clock_32;
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uint32 max_dac2_clock_32dh;
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bool secondary_head; /* presence of functions */
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bool secondary_tvout;
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bool primary_dvi;
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bool secondary_dvi;
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uint32 memory_size; /* memory (Mb) */
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uint32 mctlwtst_reg; /* memory control waitstate register */
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uint32 option_reg; /* option register */
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uint8 v3_clk_div; /* pins v3 memory and system clock division factors */
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uint8 v3_mem_type; /* pins v3 memory type info */
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} ps;
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/*mirror of the ROM (copied in driver, because may not be mapped permanently - only over fb)*/
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uint8 rom_mirror[32768];
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/*CRTC delay -> used in timing for MAVEN, depending on which CRTC is driving it*/
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uint8 crtc_delay;
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/* apsed: some configuration settings from ~/config/settings/kernel/drivers/mga.settings if exists */
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settings settings;
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struct
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{
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overlay_buffer myBuffer[MAXBUFFERS];/* scaler input buffers */
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int_buf_info myBufInfo[MAXBUFFERS]; /* extra info on scaler input buffers */
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overlay_token myToken; /* scaler is free/in use */
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benaphore lock; /* for creating buffers and aquiring overlay unit routines */
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} overlay;
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} shared_info;
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/* Read or write a value in PCI configuration space */
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typedef struct {
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uint32 magic; /* magic number to make sure the caller groks us */
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uint32 offset; /* Offset to read/write */
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uint32 size; /* Number of bytes to transfer */
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uint32 value; /* The value read or written */
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} gx00_get_set_pci;
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/* Set some boolean condition (like enabling or disabling interrupts) */
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typedef struct {
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uint32 magic; /* magic number to make sure the caller groks us */
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bool do_it; /* state to set */
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} gx00_set_bool_state;
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/* Retrieve the area_id of the kernel/accelerant shared info */
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typedef struct {
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uint32 magic; /* magic number to make sure the caller groks us */
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area_id shared_info_area; /* area_id containing the shared information */
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} gx00_get_private_data;
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/* Retrieve the device name. Usefull for when we have a file handle, but want
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to know the device name (like when we are cloning the accelerant) */
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typedef struct {
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uint32 magic; /* magic number to make sure the caller groks us */
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char *name; /* The name of the device, less the /dev root */
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} gx00_device_name;
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enum {
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GX00_WAIT_FOR_VBLANK = (1 << 0)
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};
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#if defined(__cplusplus)
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}
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#endif
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#endif
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@@ -0,0 +1,286 @@
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/* MGA registers definitions and macros for access to */
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/* apsed : merged mga_macro.h and mga_regs.c with #define for speed */
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/* PCI_config_space */
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#define MGACFG_DEVID 0x00
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#define MGACFG_DEVCTRL 0x04
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#define MGACFG_CLASS 0x08
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#define MGACFG_HEADER 0x0c
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#define MGACFG_MGABASE2 0x10
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#define MGACFG_MGABASE1 0x14
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#define MGACFG_MGABASE3 0x18 // >= MYST
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#define MGACFG_SUBSYSIDR 0x2c // >= MYST
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#define MGACFG_ROMBASE 0x30
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#define MGACFG_CAP_PTR 0x34 // >= MIL2
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#define MGACFG_INTCTRL 0x3c
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#define MGACFG_OPTION 0x40
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#define MGACFG_MGA_INDEX 0x44
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#define MGACFG_MGA_DATA 0x48
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#define MGACFG_SUBSYSIDW 0x4c // >= MYST
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#define MGACFG_OPTION2 0x50 // >= G100
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#define MGACFG_OPTION3 0x54 // >= G400
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#define MGACFG_OPTION4 0x58 // >= G400
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#define MGACFG_PM_IDENT 0xdc // >= G100
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#define MGACFG_PM_CSR 0xe0 // >= G100
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#define MGACFG_AGP_IDENT 0xf0 // >= MIL2
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#define MGACFG_AGP_STS 0xf4 // >= MIL2
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#define MGACFG_AGP_CMD 0xf8 // >= MIL2
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/*VGA registers - these are byte wide*/
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#define MGAVGA_ATTR_I 0x1FC0 // apsed as SEQ
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#define MGAVGA_ATTR_D 0x1FC1 // apsed as SEQ
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#define MGAVGA_MISCW 0x1FC2
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#define MGAVGA_SEQ_I 0x1FC4
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#define MGAVGA_SEQ_D 0x1FC5
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#define MGAVGA_DACSTAT 0x1FC7
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#define MGAVGA_FEATR 0x1FCA
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#define MGAVGA_MISCR 0x1FCC
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#define MGAVGA_GCTL_I 0x1FCE
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#define MGAVGA_GCTL_D 0x1FCF
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#define MGAVGA_CRTC_I 0x1FD4
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#define MGAVGA_CRTC_D 0x1FD5
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#define MGAVGA_INSTS1 0x1FDA
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#define MGAVGA_FEATW 0x1FDA
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#define MGAVGA_CRTCEXT_I 0x1FDE
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#define MGAVGA_CRTCEXT_D 0x1FDF
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/*DAC registers (>= g100) */
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#define MGADAC_PALWTADD 0x3C00
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#define MGADAC_PALDATA 0x3C01
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#define MGADAC_PIXRDMSK 0x3C02
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#define MGADAC_PALRDADD 0x3C03
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#define MGADAC_X_DATAREG 0x3C0A
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#define MGADAC_CURSPOSXL 0x3C0C
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#define MGADAC_CURSPOSXH 0x3C0D
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#define MGADAC_CURSPOSYL 0x3C0E
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#define MGADAC_CURSPOSYH 0x3C0F
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/*(D)AC (X) (I)ndexed registers (>= g100) */
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#define MGADXI_CURADDL 0x04
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#define MGADXI_CURADDH 0x05
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#define MGADXI_CURCTRL 0x06
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#define MGADXI_CURCOL0RED 0x08
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#define MGADXI_CURCOL0GREEN 0x09
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#define MGADXI_CURCOL0BLUE 0x0A
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#define MGADXI_CURCOL1RED 0x0C
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#define MGADXI_CURCOL1GREEN 0x0D
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#define MGADXI_CURCOL1BLUE 0x0E
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#define MGADXI_CURCOL2RED 0x10
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#define MGADXI_CURCOL2GREEN 0x11
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#define MGADXI_CURCOL2BLUE 0x12
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#define MGADXI_VREFCTRL 0x18
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#define MGADXI_MULCTRL 0x19
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#define MGADXI_PIXCLKCTRL 0x1A
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#define MGADXI_GENCTRL 0x1D
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#define MGADXI_MISCCTRL 0x1E
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#define MGADXI_PANELMODE 0x1F
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#define MGADXI_MAFCDEL 0x20
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#define MGADXI_GENIOCTRL 0x2A
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#define MGADXI_GENIODATA 0x2B
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#define MGADXI_SYSPLLM 0x2C
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#define MGADXI_SYSPLLN 0x2D
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#define MGADXI_SYSPLLP 0x2E
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#define MGADXI_SYSPLLSTAT 0x2F
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#define MGADXI_ZOOMCTRL 0x38
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#define MGADXI_SENSETEST 0x3A
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#define MGADXI_CRCREML 0x3C
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#define MGADXI_CRCREMH 0x3D
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#define MGADXI_CRCBITSEL 0x3E
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#define MGADXI_COLMSK 0x40
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#define MGADXI_COLKEY 0x42
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#define MGADXI_PIXPLLAM 0x44
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#define MGADXI_PIXPLLAN 0x45
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#define MGADXI_PIXPLLAP 0x46
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#define MGADXI_PIXPLLBM 0x48
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#define MGADXI_PIXPLLBN 0x49
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#define MGADXI_PIXPLLBP 0x4A
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#define MGADXI_PIXPLLCM 0x4C
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#define MGADXI_PIXPLLCN 0x4D
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#define MGADXI_PIXPLLCP 0x4E
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#define MGADXI_PIXPLLSTAT 0x4F
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#define MGADXI_CURCOLEXT 0x60 /*sequential from CURCOL3->15, RGB*/
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//rudolf: missing registers!
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/*(D)AC (X) (I)ndexed registers (>= g200) */
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#define MGADXI_KEYOPMODE 0x51
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#define MGADXI_COLMSK0RED 0x52
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#define MGADXI_COLMSK0GREEN 0x53
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#define MGADXI_COLMSK0BLUE 0x54
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#define MGADXI_COLKEY0RED 0x55
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#define MGADXI_COLKEY0GREEN 0x56
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#define MGADXI_COLKEY0BLUE 0x57
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/*MGA 1st CRTC registers */
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#define MGACR1_VCOUNT 0x1E20
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//end rudolf.
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/*MGA 2nd CRTC registers >= ?? TODO */
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#define MGACR2_CTL 0x3C10
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#define MGACR2_HPARAM 0x3C14
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#define MGACR2_HSYNC 0x3C18
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#define MGACR2_VPARAM 0x3C1C
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#define MGACR2_VSYNC 0x3C20
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#define MGACR2_PRELOAD 0x3C24
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#define MGACR2_STARTADD0 0x3C28
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#define MGACR2_OFFSET 0x3C40
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#define MGACR2_MISC 0x3C44
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#define MGACR2_VCOUNT 0x3C48
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#define MGACR2_DATACTL 0x3C4C
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/*MGA ACCeleration registers*/
|
||||
#define MGAACC_DWGCTL 0x1C00
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#define MGAACC_MACCESS 0x1C04
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#define MGAACC_MCTLWTST 0x1C08
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#define MGAACC_ZORG 0x1C0C
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#define MGAACC_PLNWT 0x1C1C
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#define MGAACC_BCOL 0x1C20
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#define MGAACC_FCOL 0x1C24
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#define MGAACC_XYSTRT 0x1C40
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||||
#define MGAACC_XYEND 0x1C44
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#define MGAACC_SGN 0x1C58
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||||
#define MGAACC_LEN 0x1C5C
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||||
#define MGAACC_AR0 0x1C60
|
||||
#define MGAACC_AR3 0x1C6C
|
||||
#define MGAACC_AR5 0x1C74
|
||||
#define MGAACC_CXBNDRY 0x1C80
|
||||
#define MGAACC_FXBNDRY 0x1C84
|
||||
#define MGAACC_YDSTLEN 0x1C88
|
||||
#define MGAACC_PITCH 0x1C8C
|
||||
#define MGAACC_YDST 0x1C90
|
||||
#define MGAACC_YDSTORG 0x1C94
|
||||
#define MGAACC_YTOP 0x1C98
|
||||
#define MGAACC_YBOT 0x1C9C
|
||||
#define MGAACC_CXLEFT 0x1CA0
|
||||
#define MGAACC_CXRIGHT 0x1CA4
|
||||
#define MGAACC_FXLEFT 0x1CA8
|
||||
#define MGAACC_FXRIGHT 0x1CAC
|
||||
#define MGAACC_STATUS 0x1E14
|
||||
#define MGAACC_ICLEAR 0x1E18 /* required for interrupt stuff */
|
||||
#define MGAACC_IEN 0x1E1C /* required for interrupt stuff */
|
||||
#define MGAACC_RST 0x1E40
|
||||
#define MGAACC_MEMRDBK 0x1E44
|
||||
#define MGAACC_OPMODE 0x1E54
|
||||
#define MGAACC_PRIMADDRESS 0x1E58
|
||||
#define MGAACC_PRIMEND 0x1E5C
|
||||
#define MGAACC_TEXORG 0x2C24 // >= G100
|
||||
#define MGAACC_DWGSYNC 0x2C4C // >= G200
|
||||
#define MGAACC_TEXORG1 0x2CA4 // >= G200
|
||||
#define MGAACC_TEXORG2 0x2CA8 // >= G200
|
||||
#define MGAACC_TEXORG3 0x2CAC // >= G200
|
||||
#define MGAACC_TEXORG4 0x2CB0 // >= G200
|
||||
#define MGAACC_SRCORG 0x2CB4 // >= G200
|
||||
#define MGAACC_DSTORG 0x2CB8 // >= G200
|
||||
|
||||
/*MGA BES (Back End Scaler) registers >= TODO */
|
||||
#define MGABES_A1ORG 0x3D00
|
||||
#define MGABES_A2ORG 0x3D04
|
||||
#define MGABES_B1ORG 0x3D08
|
||||
#define MGABES_B2ORG 0x3D0C
|
||||
#define MGABES_A1CORG 0x3D10
|
||||
#define MGABES_A2CORG 0x3D14
|
||||
#define MGABES_B1CORG 0x3D18
|
||||
#define MGABES_B2CORG 0x3D1C
|
||||
#define MGABES_CTL 0x3D20
|
||||
#define MGABES_PITCH 0x3D24
|
||||
#define MGABES_HCOORD 0x3D28
|
||||
#define MGABES_VCOORD 0x3D2C
|
||||
#define MGABES_HISCAL 0x3D30
|
||||
#define MGABES_VISCAL 0x3D34
|
||||
#define MGABES_HSRCST 0x3D38
|
||||
#define MGABES_HSRCEND 0x3D3C
|
||||
#define MGABES_LUMACTL 0x3D40
|
||||
#define MGABES_V1WGHT 0x3D48
|
||||
#define MGABES_V2WGHT 0x3D4C
|
||||
#define MGABES_HSRCLST 0x3D50
|
||||
#define MGABES_V1SRCLST 0x3D54
|
||||
#define MGABES_V2SRCLST 0x3D58
|
||||
#define MGABES_A1C3ORG 0x3D60
|
||||
#define MGABES_A2C3ORG 0x3D64
|
||||
#define MGABES_B1C3ORG 0x3D68
|
||||
#define MGABES_B2C3ORG 0x3D6C
|
||||
#define MGABES_GLOBCTL 0x3DC0
|
||||
#define MGABES_STATUS 0x3DC4
|
||||
|
||||
/*MAVEN registers >= TODO */
|
||||
#define MGAMAV_PIXPLLM 0x80
|
||||
#define MGAMAV_PIXPLLN 0x81
|
||||
#define MGAMAV_PIXPLLP 0x82
|
||||
#define MGAMAV_MONSET 0x8C
|
||||
#define MGAMAV_TEST 0x8D
|
||||
#define MGAMAV_MONEN 0x94
|
||||
#define MGAMAV_LASTLINEL 0x96
|
||||
#define MGAMAV_LASTLINEH 0x97
|
||||
#define MGAMAV_HSYNCLENL 0x9A
|
||||
#define MGAMAV_HSYNCLENH 0x9B
|
||||
#define MGAMAV_HSYNCSTRL 0x9C
|
||||
#define MGAMAV_HSYNCSTRH 0x9D
|
||||
#define MGAMAV_HDISPLAYL 0x9E
|
||||
#define MGAMAV_HDISPLAYH 0x9F
|
||||
#define MGAMAV_HTOTALL 0xA0
|
||||
#define MGAMAV_HTOTALH 0xA1
|
||||
#define MGAMAV_VSYNCLENL 0xA2
|
||||
#define MGAMAV_VSYNCLENH 0xA3
|
||||
#define MGAMAV_VSYNCSTRL 0xA4
|
||||
#define MGAMAV_VSYNCSTRH 0xA5
|
||||
#define MGAMAV_VDISPLAYL 0xA6
|
||||
#define MGAMAV_VDISPLAYH 0xA7
|
||||
#define MGAMAV_VTOTALL 0xA8
|
||||
#define MGAMAV_VTOTALH 0xA9
|
||||
#define MGAMAV_HVIDRSTL 0xAA
|
||||
#define MGAMAV_HVIDRSTH 0xAB
|
||||
#define MGAMAV_VVIDRSTL 0xAC
|
||||
#define MGAMAV_VVIDRSTH 0xAD
|
||||
#define MGAMAV_OUTMODE 0xB0
|
||||
#define MGAMAV_LOCK 0xB3
|
||||
#define MGAMAV_LUMA 0xB9
|
||||
#define MGAMAV_STABLE 0xBF
|
||||
|
||||
/*Macros for convenient accesses to the G400*/
|
||||
|
||||
#define MGA_REG8(r_) ((vuint8 *)regs)[(r_)]
|
||||
#define MGA_REG32(r_) ((vuint32 *)regs)[(r_) >> 2]
|
||||
|
||||
/*read and write to PCI config space*/
|
||||
#define CFGR(A) (gx00_pci_access.offset=MGACFG_##A, ioctl(fd,GX00_GET_PCI, &gx00_pci_access,sizeof(gx00_pci_access)), gx00_pci_access.value)
|
||||
#define CFGW(A,B) (gx00_pci_access.offset=MGACFG_##A, gx00_pci_access.value = B, ioctl(fd,GX00_SET_PCI,&gx00_pci_access,sizeof(gx00_pci_access)))
|
||||
|
||||
/*read and write from the dac registers*/
|
||||
#define DACR(A) (MGA_REG8(MGADAC_##A))
|
||||
#define DACW(A,B) (MGA_REG8(MGADAC_##A)=B)
|
||||
|
||||
/*read and write from the dac index register*/
|
||||
#define DXIR(A) (DACW(PALWTADD,MGADXI_##A),DACR(X_DATAREG))
|
||||
#define DXIW(A,B) (DACW(PALWTADD,MGADXI_##A),DACW(X_DATAREG,B))
|
||||
|
||||
/*read and write from the vga registers*/
|
||||
#define VGAR(A) (MGA_REG8(MGAVGA_##A))
|
||||
#define VGAW(A,B) (MGA_REG8(MGAVGA_##A)=B)
|
||||
|
||||
/*read and write from the indexed vga registers*/
|
||||
#define VGAR_I(A,B) (VGAW(A##_I,B),VGAR(A##_D))
|
||||
#define VGAW_I(A,B,C) (VGAW(A##_I,B),VGAW(A##_D,C))
|
||||
|
||||
/*read and write from the powergraphics registers*/
|
||||
#define ACCR(A) (MGA_REG32(MGAACC_##A))
|
||||
#define ACCW(A,B) (MGA_REG32(MGAACC_##A)=B)
|
||||
#define ACCGO(A,B) (MGA_REG32(MGAACC_##A + 0x0100)=B)
|
||||
|
||||
/*read and write from the backend scaler registers*/
|
||||
#define BESR(A) (MGA_REG32(MGABES_##A))
|
||||
#define BESW(A,B) (MGA_REG32(MGABES_##A)=B)
|
||||
|
||||
/*read and write from first CRTC*/
|
||||
#define CR1R(A) (MGA_REG32(MGACR1_##A))
|
||||
#define CR1W(A,B) (MGA_REG32(MGACR1_##A)=B)
|
||||
|
||||
/*read and write from second CRTC*/
|
||||
#define CR2R(A) (MGA_REG32(MGACR2_##A))
|
||||
#define CR2W(A,B) (MGA_REG32(MGACR2_##A)=B)
|
||||
|
||||
/*read and write from maven*/
|
||||
#define MAVR(A) (i2c_maven_read (MGAMAV_##A ))
|
||||
#define MAVW(A,B) (i2c_maven_write(MGAMAV_##A ,B))
|
||||
#define MAVRW(A) (i2c_maven_read (MGAMAV_##A )|(i2c_maven_read(MGAMAV_##A +1)<<8))
|
||||
#define MAVWW(A,B) (i2c_maven_write(MGAMAV_##A ,B &0xFF),i2c_maven_write(MGAMAV_##A +1,B >>8))
|
||||
#define MAVWWP(A,B) (i2c_maven_write(A ,B &0xFF),i2c_maven_write(A +1,B >>8))
|
||||
Reference in New Issue
Block a user