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added colordepth and CRTC FIFO limit programming. You can now switch colorspaces on the fly, but colors probably mess-up because of still lacking colorpalette programming.

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git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@13745 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen
2005-07-18 11:39:11 +00:00
parent 83d1f41819
commit 381288838b
2 changed files with 43 additions and 27 deletions
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src/add-ons/accelerants/via/SetDisplayMode.c
+5 -5
View File
@@ -155,22 +155,22 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
case B_CMAP8: case B_CMAP8:
colour_depth1 = 8; colour_depth1 = 8;
// head1_mode(BPP8, 1.0); // head1_mode(BPP8, 1.0);
// head1_depth(BPP8); head1_depth(BPP8);
break; break;
case B_RGB15_LITTLE: case B_RGB15_LITTLE:
colour_depth1 = 16; colour_depth1 = 16;
// head1_mode(BPP15, 1.0); // head1_mode(BPP15, 1.0);
// head1_depth(BPP15); head1_depth(BPP15);
break; break;
case B_RGB16_LITTLE: case B_RGB16_LITTLE:
colour_depth1 = 16; colour_depth1 = 16;
// head1_mode(BPP16, 1.0); // head1_mode(BPP16, 1.0);
// head1_depth(BPP16); head1_depth(BPP16);
break; break;
case B_RGB32_LITTLE: case B_RGB32_LITTLE:
colour_depth1 = 32; colour_depth1 = 32;
// head1_mode(BPP32, 1.0); // head1_mode(BPP32, 1.0);
// head1_depth(BPP32); head1_depth(BPP32);
break; break;
} }
/*set the colour depth for CRTC2 and DAC2 */ /*set the colour depth for CRTC2 and DAC2 */
@@ -286,7 +286,7 @@ status = B_OK;
/* set the colour depth for CRTC1 and the DAC */ /* set the colour depth for CRTC1 and the DAC */
/* first set the colordepth */ /* first set the colordepth */
// head1_depth(colour_mode); head1_depth(colour_mode);
/* then(!) program the PAL (<8bit colordepth does not support 8bit PAL) */ /* then(!) program the PAL (<8bit colordepth does not support 8bit PAL) */
// head1_mode(colour_mode,1.0); // head1_mode(colour_mode,1.0);
src/add-ons/accelerants/via/engine/crtc.c
+38 -22
View File
@@ -80,6 +80,7 @@ status_t eng_crtc_validate_timing(
/*set a mode line - inputs are in pixels*/ /*set a mode line - inputs are in pixels*/
status_t eng_crtc_set_timing(display_mode target) status_t eng_crtc_set_timing(display_mode target)
{ {
uint16 fifolimit = 0;
uint8 temp; uint8 temp;
uint32 htotal; /*total horizontal total VCLKs*/ uint32 htotal; /*total horizontal total VCLKs*/
@@ -269,6 +270,29 @@ status_t eng_crtc_set_timing(display_mode target)
ENG_REG8(RG8_MISCW) = temp; ENG_REG8(RG8_MISCW) = temp;
LOG(2,(", MISC reg readback: $%02x\n", ENG_REG8(RG8_MISCR))); LOG(2,(", MISC reg readback: $%02x\n", ENG_REG8(RG8_MISCR)));
/* setup CRTC FIFO depth, method 'extrapolated' from VBE BIOS behaviour */
switch (target.space)
{
case B_CMAP8:
fifolimit = 0x0001;
break;
case B_RGB15_LITTLE:
case B_RGB16_LITTLE:
fifolimit = 0x0002;
break;
case B_RGB24_LITTLE:
fifolimit = 0x0003;
break;
case B_RGB32_LITTLE:
fifolimit = 0x0004;
break;
}
fifolimit *= target.timing.h_display;
fifolimit >>= 4;
fifolimit += 4;
SEQW(FETCHCNTLO, (fifolimit & 0x00fe));
SEQW(FETCHCNTHI, (((SEQR(FETCHCNTHI)) & 0xfc) | ((fifolimit & 0x0300) >> 8)));
} }
/* always disable interlaced operation */ /* always disable interlaced operation */
@@ -396,43 +420,35 @@ status_t eng_crtc_set_timing(display_mode target)
status_t eng_crtc_depth(int mode) status_t eng_crtc_depth(int mode)
{ {
uint8 viddelay = 0; uint8 genctrl = 0;
uint32 genctrl = 0;
/* set VCLK scaling */ /* set VCLK scaling */
switch(mode) switch(mode)
{ {
case BPP8: case BPP8:
viddelay = 0x01; /* bits unknown (yet): 'direct mode' */
/* genctrl b4 & b5 reset: 'direct mode' */ genctrl = 0x22; //%0010 0010
genctrl = 0x00101100;
break; break;
case BPP15: case BPP15:
viddelay = 0x02; /* bits unknown (yet): 'indirect mode' (via colorpalette?) */
/* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ genctrl = 0xb6; //%1011 0110
genctrl = 0x00100130;
break; break;
case BPP16: case BPP16:
viddelay = 0x02; /* bits unknown (yet): 'indirect mode' (via colorpalette?) */
/* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ genctrl = 0xb6; //%1011 0110
genctrl = 0x00101130;
break; break;
case BPP24: case BPP24:
viddelay = 0x03; /* bits unknown (yet): 'indirect mode' (via colorpalette?) */
/* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ //fixme: unknown what to set yet..
genctrl = 0x00100130; genctrl = 0x00;
break; break;
case BPP32: case BPP32:
viddelay = 0x03; /* bits unknown (yet): 'indirect mode' (via colorpalette?) */
/* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ genctrl = 0xae; //%1010 1110
genctrl = 0x00101130;
break; break;
} }
/* enable access to primary head */ /* setup bytes per pixel, and direct/indirect mode */
set_crtc_owner(0); SEQW(COLDEPTH, genctrl);
CRTCW(PIXEL, ((CRTCR(PIXEL) & 0xfc) | viddelay));
DACW(GENCTRL, genctrl);
return B_OK; return B_OK;
} }