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Accidently used level 2 cache format to print out level 1 instruction cache

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on AMD and other CPUs - thanks to BiPolar for reporting this!


git-svn-id: file:///srv/svn/repos/haiku/trunk/current@10354 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Axel Dörfler
2004-12-03 08:25:34 +00:00
parent 6e6f8fff95
commit 7c012c2316
1 changed files with 1 additions and 1 deletions
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src/apps/bin/sysinfo.c
+1 -1
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@@ -191,7 +191,7 @@ print_cache_descriptors(int32 cpu)
print_TLB(info.regs.ebx, info.regs.eax ? "4K-byte" : NULL);
print_level1_cache(info.regs.ecx, "L1 inst cache");
print_level2_cache(info.regs.edx, "L1 data cache");
print_level1_cache(info.regs.edx, "L1 data cache");
get_cpuid(&info, 0x80000006, cpu);
print_level2_cache(info.regs.ecx, "L2 cache");