arm64/uefi: Perform MMU maintenance when TBBR1_EL1 is enabled.

* Cache & TLB maintenance need to be performed when TBBR1_EL1 is
  enabled, not when it is setup.
* Boots all the way into the kernel (and dies in the kernel
  debugger) on M1 Max hardware under virtualization.
* Add more details comments on the reasoning behind the process.

Change-Id: Ib4b5aa3bbae71d69169575c06c7cd75d616307d9
Reviewed-on: https://review.haiku-os.org/c/haiku/+/8084
Haiku-Format: Haiku-format Bot <[email protected]>
Reviewed-by: Fredrik Holmqvist <[email protected]>
Reviewed-by: David Karoly <[email protected]>
Tested-by: Commit checker robot <[email protected]>

src/system/boot/platform/efi/arch/arm64/arch_mmu.cpp

@@ -122,7 +122,14 @@ void arch_mmu_setup_EL1(uint64 tcr) {
 	// TODO: Compiler dependency?
 	tcr |= TCR_T1SZ(__builtin_popcountl(KERNEL_BASE));
 
+	// Flush the cache so that we don't receive unexpected writebacks later.
+	_arch_cache_clean_poc();
+
 	WRITE_SPECIALREG(TCR_EL1, tcr);
+
+	// Invalidate all TLB entries. Also ensures that all memory traffic has
+	// resolved, and flushes the instruction pipeline.
+	_arch_mmu_invalidate_tlb_all(arch_exception_level());
 }
 
 
@@ -348,9 +355,7 @@ arch_mmu_allocate_kernel_page_tables(void)
 	if (page == NULL) {
 		page = CurrentRegime.AllocatePage();
 		if (page != NULL) {
-			arch_cache_disable();
 			WRITE_SPECIALREG(TTBR1_EL1, page);
-			arch_cache_enable();
 		} else {
 			panic("Not enough memory for kernel initial page\n");
 		}