intel extreme: skylake sets color, base and address, no resolution and refresh yet

This commit is contained in:
Rudolf Cornelissen
2021-10-23 17:13:43 +00:00
parent 393c7b8b5c
commit 994794f2d4
6 changed files with 57 additions and 11 deletions
@@ -762,6 +762,14 @@ struct intel_free_graphics_memory {
#define DISPLAY_CONTROL_RGB15 (4UL << 26)
#define DISPLAY_CONTROL_RGB16 (5UL << 26)
#define DISPLAY_CONTROL_RGB32 (6UL << 26)
#define DISPLAY_CONTROL_RGB64 (0x0cUL << 26)
// Skylake
#define DISPLAY_CONTROL_COLOR_MASK_SKY (0x0fUL << 24)
#define DISPLAY_CONTROL_CMAP8_SKY (0x0cUL << 24)
#define DISPLAY_CONTROL_RGB15_SKY (0x0eUL << 24)
#define DISPLAY_CONTROL_RGB16_SKY (0x0eUL << 24)
#define DISPLAY_CONTROL_RGB32_SKY (0x04UL << 24)
#define DISPLAY_CONTROL_RGB64_SKY (0x06UL << 24)
// INTEL_DISPLAY_A_PIPE_CONTROL ILK+
#define INTEL_PIPE_DITHER_TYPE_MASK (0x0000000c)
@@ -38,12 +38,21 @@ void
program_pipe_color_modes(uint32 colorMode)
{
// All pipes get the same color mode
write32(INTEL_DISPLAY_A_CONTROL, (read32(INTEL_DISPLAY_A_CONTROL)
if (gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_LAKE)) {
write32(INTEL_DISPLAY_A_CONTROL, (read32(INTEL_DISPLAY_A_CONTROL)
& ~(DISPLAY_CONTROL_COLOR_MASK_SKY | DISPLAY_CONTROL_GAMMA))
| colorMode);
write32(INTEL_DISPLAY_B_CONTROL, (read32(INTEL_DISPLAY_B_CONTROL)
& ~(DISPLAY_CONTROL_COLOR_MASK_SKY | DISPLAY_CONTROL_GAMMA))
| colorMode);
} else {
write32(INTEL_DISPLAY_A_CONTROL, (read32(INTEL_DISPLAY_A_CONTROL)
& ~(DISPLAY_CONTROL_COLOR_MASK | DISPLAY_CONTROL_GAMMA))
| colorMode);
write32(INTEL_DISPLAY_B_CONTROL, (read32(INTEL_DISPLAY_B_CONTROL)
| colorMode);
write32(INTEL_DISPLAY_B_CONTROL, (read32(INTEL_DISPLAY_B_CONTROL)
& ~(DISPLAY_CONTROL_COLOR_MASK | DISPLAY_CONTROL_GAMMA))
| colorMode);
| colorMode);
}
}
@@ -232,6 +232,11 @@ intel_wait_engine_idle(void)
{
CALLED();
// Skylake acc engine not yet functional (stalls)
if (gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_LAKE)) {
return;
}
{
QueueCommands queue(gInfo->shared_info->primary_ring_buffer);
queue.PutFlush();
+29 -6
View File
@@ -48,23 +48,39 @@ get_color_space_format(const display_mode &mode, uint32 &colorMode,
switch (mode.space) {
case B_RGB32_LITTLE:
colorMode = DISPLAY_CONTROL_RGB32;
if (gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_LAKE)) {
colorMode = DISPLAY_CONTROL_RGB32_SKY;
} else {
colorMode = DISPLAY_CONTROL_RGB32;
}
bytesPerPixel = 4;
bitsPerPixel = 32;
break;
case B_RGB16_LITTLE:
colorMode = DISPLAY_CONTROL_RGB16;
if (gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_LAKE)) {
colorMode = DISPLAY_CONTROL_RGB16_SKY;
} else {
colorMode = DISPLAY_CONTROL_RGB16;
}
bytesPerPixel = 2;
bitsPerPixel = 16;
break;
case B_RGB15_LITTLE:
colorMode = DISPLAY_CONTROL_RGB15;
if (gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_LAKE)) {
colorMode = DISPLAY_CONTROL_RGB15_SKY;
} else {
colorMode = DISPLAY_CONTROL_RGB15;
}
bytesPerPixel = 2;
bitsPerPixel = 15;
break;
case B_CMAP8:
default:
colorMode = DISPLAY_CONTROL_CMAP8;
if (gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_LAKE)) {
colorMode = DISPLAY_CONTROL_CMAP8_SKY;
} else {
colorMode = DISPLAY_CONTROL_CMAP8;
}
bytesPerPixel = 1;
bitsPerPixel = 8;
break;
@@ -121,8 +137,10 @@ set_frame_buffer_registers(uint32 offset)
|| sharedInfo.device_type.InGroup(INTEL_GROUP_G4x)
|| sharedInfo.device_type.InGroup(INTEL_GROUP_ILK)
|| sharedInfo.device_type.InFamily(INTEL_FAMILY_SER5)
|| sharedInfo.device_type.InFamily(INTEL_FAMILY_LAKE)
|| sharedInfo.device_type.InFamily(INTEL_FAMILY_SOC0)) {
if (sharedInfo.device_type.InGroup(INTEL_GROUP_HAS)) {
// || sharedInfo.device_type.InGroup(INTEL_GROUP_SKY)) {
write32(INTEL_DISPLAY_A_OFFSET_HAS + offset,
((uint32)mode.v_display_start << 16)
| (uint32)mode.h_display_start);
@@ -463,8 +481,13 @@ intel_set_display_mode(display_mode* mode)
// Always set both pipes, just in case
// TODO rework this when we get multiple head support with different
// resolutions
write32(INTEL_DISPLAY_A_BYTES_PER_ROW, bytesPerRow);
write32(INTEL_DISPLAY_B_BYTES_PER_ROW, bytesPerRow);
if (sharedInfo.device_type.InFamily(INTEL_FAMILY_LAKE)) {
write32(INTEL_DISPLAY_A_BYTES_PER_ROW, bytesPerRow >> 6);
write32(INTEL_DISPLAY_B_BYTES_PER_ROW, bytesPerRow >> 6);
} else {
write32(INTEL_DISPLAY_A_BYTES_PER_ROW, bytesPerRow);
write32(INTEL_DISPLAY_B_BYTES_PER_ROW, bytesPerRow);
}
// update shared info
sharedInfo.current_mode = target;
@@ -132,7 +132,7 @@ const struct supported_device {
{0x1904, 0x190a, INTEL_MODEL_SKYS, "Skylake GT1"},
{0x1904, 0x190b, INTEL_MODEL_SKY, "Skylake GT1"},
{0x1904, 0x190e, INTEL_MODEL_SKYM, "Skylake GT1"},
{0x1904, 0x1912, INTEL_MODEL_SKY, "Skylake GT2"},
{0x191f, 0x1912, INTEL_MODEL_SKY, "Skylake GT2"}, // confirmed
{0x1904, 0x1916, INTEL_MODEL_SKYM, "Skylake GT2"},
{0x1904, 0x191a, INTEL_MODEL_SKYS, "Skylake GT2"},
{0x1904, 0x191b, INTEL_MODEL_SKY, "Skylake GT2"},
@@ -105,6 +105,7 @@ const struct supported_device {
{0x0d26, INTEL_MODEL_HASM, "Haswell Mobile"},
{0x0a16, INTEL_MODEL_HASM, "Haswell Mobile"},
{0x1912, INTEL_MODEL_SKY, "Skylake GT2"}, // testing..
#if 0
// The driver does not make any attempt to handle this modern hardware.
// Better let VESA/UEFI do it.