* Small style fix to Calibration diff var and PLLCRTCGrab stored var
* Repair incorrect DCCG operation at end of PLLSet git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42149 a95241bf-73f2-0310-859d-f6bbb57e9c96
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@@ -89,8 +89,6 @@ PLLCalculate(uint32 pixelClock, uint16 *reference, uint16 *feedback,
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for (referenceDiv = 1; referenceDiv <= REF_DIV_LIMIT; referenceDiv++) {
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uint32 diff;
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feedbackDiv = (uint32)((ratio * postDiv * referenceDiv) + 0.5);
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if (feedbackDiv >= FB_DIV_LIMIT)
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@@ -98,7 +96,7 @@ PLLCalculate(uint32 pixelClock, uint16 *reference, uint16 *feedback,
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if (feedbackDiv > (500 + (13 * referenceDiv))) // rv6x0 limit
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break;
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diff = abs(pixelClock - (feedbackDiv
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uint32 diff = abs(pixelClock - (feedbackDiv
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* gInfo->shared_info->pll_info.reference_frequency)
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/ (postDiv * referenceDiv));
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@@ -323,7 +321,7 @@ PLLSet(uint8 pllIndex, uint32 pixelClock)
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PLLCRTCGrab(pllIndex, false);
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if (hasDccg)
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DCCGCLKSet(pllIndex, RV620_DCCGCLK_RELEASE);
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DCCGCLKSet(pllIndex, RV620_DCCGCLK_GRAB);
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TRACE("%s: PLLSet exit\n", __func__);
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return B_OK;
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@@ -365,8 +363,6 @@ PLLCalibrate(uint8 pllIndex)
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void
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PLLCRTCGrab(uint8 pllIndex, bool crt2)
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{
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uint32 stored;
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bool pll2IsCurrent;
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if (!crt2) {
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@@ -384,7 +380,7 @@ PLLCRTCGrab(uint8 pllIndex, bool crt2)
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/* if the current pll is not active, then poke it just enough to flip
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* owners */
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if (!pll2IsCurrent) {
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stored = read32PLL(P1PLL_CNTL);
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uint32 stored = read32PLL(P1PLL_CNTL);
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if (stored & 0x03) {
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write32PLLAtMask(P1PLL_CNTL, 0, 0x03);
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@@ -393,7 +389,7 @@ PLLCRTCGrab(uint8 pllIndex, bool crt2)
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}
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} else {
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stored = read32PLL(P2PLL_CNTL);
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uint32 stored = read32PLL(P2PLL_CNTL);
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if (stored & 0x03) {
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write32PLLAtMask(P2PLL_CNTL, 0, 0x03);
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@@ -404,6 +400,8 @@ PLLCRTCGrab(uint8 pllIndex, bool crt2)
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}
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// See if card has a DCCG available that we need to lock to
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// the PLL clock. No one seems really sure what DCCG is.
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bool
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DCCGCLKAvailable(uint8 pllIndex)
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{
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