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* Small style fix to Calibration diff var and PLLCRTCGrab stored var

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* Repair incorrect DCCG operation at end of PLLSet


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42149 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Alexander von Gluck IV
2011-06-13 14:46:52 +00:00
parent f1ec739ed7
commit a604c04965
1 changed files with 6 additions and 8 deletions
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src/add-ons/accelerants/radeon_hd/pll.cpp
+6 -8
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@@ -89,8 +89,6 @@ PLLCalculate(uint32 pixelClock, uint16 *reference, uint16 *feedback,
for (referenceDiv = 1; referenceDiv <= REF_DIV_LIMIT; referenceDiv++) { for (referenceDiv = 1; referenceDiv <= REF_DIV_LIMIT; referenceDiv++) {
uint32 diff;
feedbackDiv = (uint32)((ratio * postDiv * referenceDiv) + 0.5); feedbackDiv = (uint32)((ratio * postDiv * referenceDiv) + 0.5);
if (feedbackDiv >= FB_DIV_LIMIT) if (feedbackDiv >= FB_DIV_LIMIT)
@@ -98,7 +96,7 @@ PLLCalculate(uint32 pixelClock, uint16 *reference, uint16 *feedback,
if (feedbackDiv > (500 + (13 * referenceDiv))) // rv6x0 limit if (feedbackDiv > (500 + (13 * referenceDiv))) // rv6x0 limit
break; break;
diff = abs(pixelClock - (feedbackDiv uint32 diff = abs(pixelClock - (feedbackDiv
* gInfo->shared_info->pll_info.reference_frequency) * gInfo->shared_info->pll_info.reference_frequency)
/ (postDiv * referenceDiv)); / (postDiv * referenceDiv));
@@ -323,7 +321,7 @@ PLLSet(uint8 pllIndex, uint32 pixelClock)
PLLCRTCGrab(pllIndex, false); PLLCRTCGrab(pllIndex, false);
if (hasDccg) if (hasDccg)
DCCGCLKSet(pllIndex, RV620_DCCGCLK_RELEASE); DCCGCLKSet(pllIndex, RV620_DCCGCLK_GRAB);
TRACE("%s: PLLSet exit\n", __func__); TRACE("%s: PLLSet exit\n", __func__);
return B_OK; return B_OK;
@@ -365,8 +363,6 @@ PLLCalibrate(uint8 pllIndex)
void void
PLLCRTCGrab(uint8 pllIndex, bool crt2) PLLCRTCGrab(uint8 pllIndex, bool crt2)
{ {
uint32 stored;
bool pll2IsCurrent; bool pll2IsCurrent;
if (!crt2) { if (!crt2) {
@@ -384,7 +380,7 @@ PLLCRTCGrab(uint8 pllIndex, bool crt2)
/* if the current pll is not active, then poke it just enough to flip /* if the current pll is not active, then poke it just enough to flip
* owners */ * owners */
if (!pll2IsCurrent) { if (!pll2IsCurrent) {
stored = read32PLL(P1PLL_CNTL); uint32 stored = read32PLL(P1PLL_CNTL);
if (stored & 0x03) { if (stored & 0x03) {
write32PLLAtMask(P1PLL_CNTL, 0, 0x03); write32PLLAtMask(P1PLL_CNTL, 0, 0x03);
@@ -393,7 +389,7 @@ PLLCRTCGrab(uint8 pllIndex, bool crt2)
} }
} else { } else {
stored = read32PLL(P2PLL_CNTL); uint32 stored = read32PLL(P2PLL_CNTL);
if (stored & 0x03) { if (stored & 0x03) {
write32PLLAtMask(P2PLL_CNTL, 0, 0x03); write32PLLAtMask(P2PLL_CNTL, 0, 0x03);
@@ -404,6 +400,8 @@ PLLCRTCGrab(uint8 pllIndex, bool crt2)
} }
// See if card has a DCCG available that we need to lock to
// the PLL clock. No one seems really sure what DCCG is.
bool bool
DCCGCLKAvailable(uint8 pllIndex) DCCGCLKAvailable(uint8 pllIndex)
{ {