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added some register info I found out concerning 2D and 3D surfaces, useable as backup if programming doesn't work via the FIFO (PIO mode) or cmd buffer (DMA mode).

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git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@12862 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen
2005-05-28 11:35:42 +00:00
parent 67c26792aa
commit e09808e0d4
1 changed files with 8 additions and 0 deletions
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src/add-ons/accelerants/nvidia/engine/nv_acc.c
+8
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@@ -777,17 +777,25 @@ status_t nv_acc_init()
case NV04A:
case NV10A:
/* location of active screen in framebuffer */
/* (confirmed NV05: OFFSET0 is 2D destination buffer offset) */
ACCW(OFFSET0, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));
/* (confirmed NV05: OFFSET1 is 2D source buffer offset) */
ACCW(OFFSET1, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));
/* (confirmed NV05: OFFSET2 is 3D color buffer offset) */
ACCW(OFFSET2, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));
/* (confirmed NV05: OFFSET3 is 3D depth buffer offset) */
ACCW(OFFSET3, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));
ACCW(OFFSET4, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));
ACCW(OFFSET5, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));
/* setup buffer pitch */
/* (confirmed NV05: PITCH0 is 2D destination buffer pitch) */
ACCW(PITCH0, (si->fbc.bytes_per_row & 0x0000ffff));
/* (confirmed NV05: PITCH1 is 2D source buffer pitch) */
ACCW(PITCH1, (si->fbc.bytes_per_row & 0x0000ffff));
/* (confirmed NV05: PITCH2 is 3D color buffer pitch) */
ACCW(PITCH2, (si->fbc.bytes_per_row & 0x0000ffff));
/* (confirmed NV05: PITCH3 is 3D depth buffer pitch) */
ACCW(PITCH3, (si->fbc.bytes_per_row & 0x0000ffff));
ACCW(PITCH4, (si->fbc.bytes_per_row & 0x0000ffff));
break;