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intel_extreme: program both pll divisors

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This commit is contained in:
Alexander von Gluck IV
2015-11-26 22:57:57 -06:00
parent 7217bb117b
commit f6623f4d99
1 changed files with 12 additions and 0 deletions
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src/add-ons/accelerants/intel_extreme/Pipes.cpp
+12
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@@ -185,11 +185,17 @@ Pipe::ConfigureTimings(const pll_divisors& divisors, uint32 pixelClock,
write32(pllMD, (0 << 24) | ((pixelMultiply - 1) << 8));
}
// XXX: For now we assume no LVDS downclocking and program the same divisor
// value to both divisor 0 (standard) and 1 (reduced divisor)
if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_IGD)) {
write32(pllDivisorA, (((1 << divisors.n) << DISPLAY_PLL_N_DIVISOR_SHIFT)
& DISPLAY_PLL_IGD_N_DIVISOR_MASK)
| (((divisors.m2 - 2) << DISPLAY_PLL_M2_DIVISOR_SHIFT)
& DISPLAY_PLL_IGD_M2_DIVISOR_MASK));
write32(pllDivisorB, (((1 << divisors.n) << DISPLAY_PLL_N_DIVISOR_SHIFT)
& DISPLAY_PLL_IGD_N_DIVISOR_MASK)
| (((divisors.m2 - 2) << DISPLAY_PLL_M2_DIVISOR_SHIFT)
& DISPLAY_PLL_IGD_M2_DIVISOR_MASK));
} else {
write32(pllDivisorA, (((divisors.n - 2) << DISPLAY_PLL_N_DIVISOR_SHIFT)
& DISPLAY_PLL_N_DIVISOR_MASK)
@@ -197,6 +203,12 @@ Pipe::ConfigureTimings(const pll_divisors& divisors, uint32 pixelClock,
& DISPLAY_PLL_M1_DIVISOR_MASK)
| (((divisors.m2 - 2) << DISPLAY_PLL_M2_DIVISOR_SHIFT)
& DISPLAY_PLL_M2_DIVISOR_MASK));
write32(pllDivisorB, (((divisors.n - 2) << DISPLAY_PLL_N_DIVISOR_SHIFT)
& DISPLAY_PLL_N_DIVISOR_MASK)
| (((divisors.m1 - 2) << DISPLAY_PLL_M1_DIVISOR_SHIFT)
& DISPLAY_PLL_M1_DIVISOR_MASK)
| (((divisors.m2 - 2) << DISPLAY_PLL_M2_DIVISOR_SHIFT)
& DISPLAY_PLL_M2_DIVISOR_MASK));
}
uint32 pll = DISPLAY_PLL_ENABLED | DISPLAY_PLL_NO_VGA_CONTROL | extraFlags;