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NVidia: 64bit fixes.

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This commit is contained in:
Adrien Destugues
2014-10-19 12:51:52 +00:00
parent c8113d4d63
commit dc234e798d
7 changed files with 117 additions and 103 deletions
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src/add-ons/accelerants/nvidia/Overlay.c
+19 -22
View File
@@ -68,18 +68,20 @@ uint32 OVERLAY_SUPPORTED_FEATURES(uint32 a_color_space)
}
}
const overlay_buffer *ALLOCATE_OVERLAY_BUFFER(color_space cs, uint16 width, uint16 height)
const overlay_buffer *ALLOCATE_OVERLAY_BUFFER(color_space cs, uint16 width,
uint16 height)
{
int offset = 0; /* used to determine next buffer to create */
uint32 adress, adress2, temp32; /* used to calculate buffer adresses */
uintptr_t adress, adress2, temp32; /* used to calculate buffer adresses */
uint32 oldsize = 0; /* used to 'squeeze' new buffers between already existing ones */
int cnt; /* loopcounter */
/* acquire the shared benaphore */
AQUIRE_BEN(si->overlay.lock)
LOG(4,("Overlay: cardRAM_start = $%08x\n",(uint32)((uint8*)si->framebuffer)));
LOG(4,("Overlay: cardRAM_start_DMA = $%08x\n",(uint32)((uint8*)si->framebuffer_pci)));
LOG(4, ("Overlay: cardRAM_start = $%p\n", (uint8*)si->framebuffer));
LOG(4, ("Overlay: cardRAM_start_DMA = $%p\n", (uint8*)si->framebuffer_pci));
LOG(4, ("Overlay: cardRAM_size = %3.3fMb\n", (si->ps.memory_size / (1024.0 * 1024.0))));
/* find first empty slot (room for another buffer?) */
@@ -100,9 +102,7 @@ const overlay_buffer *ALLOCATE_OVERLAY_BUFFER(color_space cs, uint16 width, uint
{
/* check if slopspace is needed: RIVA128 and TNT need ~0x000f. */
si->overlay.myBuffer[offset].width = ((width + 0x000f) & ~0x000f);
}
else
{
} else {
/* check if slopspace is needed: GeForce need ~0x001f. */
/* fixme:
* update needed for GF DVDmax support to adhere to CRTC2 constraints?? */
@@ -208,14 +208,14 @@ const overlay_buffer *ALLOCATE_OVERLAY_BUFFER(color_space cs, uint16 width, uint
* Driver setup is as follows:
* card base: - hardware cursor bitmap (if used),
* directly above - screen memory for both heads */
adress2 = (((uint32)((uint8*)si->fbc.frame_buffer)) + /* cursor already included here */
adress2 = (((uintptr_t)((uint8*)si->fbc.frame_buffer)) + /* cursor already included here */
(si->fbc.bytes_per_row * si->dm.virtual_height)); /* size in bytes of screen(s) */
LOG(4, ("Overlay: first free cardRAM virtual adress $%08x\n", adress2));
/* calculate 'preliminary' buffer size including slopspace */
oldsize = si->overlay.myBufInfo[offset].size;
si->overlay.myBufInfo[offset].size =
si->overlay.myBuffer[offset].bytes_per_row * si->overlay.myBuffer[offset].height;
si->overlay.myBufInfo[offset].size
= si->overlay.myBuffer[offset].bytes_per_row * si->overlay.myBuffer[offset].height;
/* calculate virtual memory adress that would be needed for a new bitmap */
/* NOTE to app programmers:
@@ -228,7 +228,7 @@ const overlay_buffer *ALLOCATE_OVERLAY_BUFFER(color_space cs, uint16 width, uint
* If you switch now to settings: 1600x1200x32bit (single head) the app needs to fallback to
* bitmap output or maybe single buffered overlay output if small bitmaps are used. */
adress = (((uint32)((uint8*)si->framebuffer)) + si->ps.memory_size);
adress = (((uintptr_t)((uint8*)si->framebuffer)) + si->ps.memory_size);
/* Keep some extra distance as a workaround for certain bugs (see
* DriverInterface.h for an explanation). */
if (si->ps.card_arch < NV40A)
@@ -246,7 +246,7 @@ const overlay_buffer *ALLOCATE_OVERLAY_BUFFER(color_space cs, uint16 width, uint
/* Check if we need to modify the buffers starting adress and thus the size */
/* calculate 'would be' cardRAM offset */
temp32 = (adress - ((uint32)((vuint32 *)si->framebuffer)));
temp32 = (adress - ((uintptr_t)((vuint32 *)si->framebuffer)));
/* check if it is aligned */
if (temp32 != (temp32 & 0xfffffff0))
{
@@ -285,9 +285,7 @@ const overlay_buffer *ALLOCATE_OVERLAY_BUFFER(color_space cs, uint16 width, uint
"Overlay: resetting it to virtual adress $%08x and size $%08x\n", adress,oldsize));
/* force exiting the FOR loop */
cnt = MAXBUFFERS;
}
else
{
} else {
/* nogo, sorry */
LOG(4, ("Overlay: Other buffer(s) exist after this one:\n"
"Overlay: not enough space to 'squeeze' this one in, aborted\n"));
@@ -319,7 +317,7 @@ const overlay_buffer *ALLOCATE_OVERLAY_BUFFER(color_space cs, uint16 width, uint
si->overlay.myBuffer[offset].buffer = (void *) adress;
/* calculate physical memory adress (for dma use) */
adress = (((uint32)((uint8*)si->framebuffer_pci)) + si->ps.memory_size);
adress = (((uintptr_t)((uint8*)si->framebuffer_pci)) + si->ps.memory_size);
/* Keep some extra distance as a workaround for certain bugs (see
* DriverInterface.h for an explanation). */
if (si->ps.card_arch < NV40A)
@@ -334,19 +332,17 @@ const overlay_buffer *ALLOCATE_OVERLAY_BUFFER(color_space cs, uint16 width, uint
/* this adress is already aligned to the scaler's requirements (via the already modified sizes) */
si->overlay.myBuffer[offset].buffer_dma = (void *) adress;
LOG(4,("Overlay: New buffer: addr $%08x, dma_addr $%08x, color space $%08x\n",
(uint32)((uint8*)si->overlay.myBuffer[offset].buffer),
(uint32)((uint8*)si->overlay.myBuffer[offset].buffer_dma), cs));
LOG(4, ("Overlay: New buffer: addr $%p, dma_addr $%p, color space $%08x\n",
(uint8*)si->overlay.myBuffer[offset].buffer,
(uint8*)si->overlay.myBuffer[offset].buffer_dma, cs));
LOG(4, ("Overlay: New buffer's size is $%08x\n", si->overlay.myBufInfo[offset].size));
/* release the shared benaphore */
RELEASE_BEN(si->overlay.lock)
return &si->overlay.myBuffer[offset];
}
else
} else {
/* sorry, no more room for buffers */
{
LOG(4, ("Overlay: Sorry, no more space for buffers: aborted\n"));
/* release the shared benaphore */
@@ -356,6 +352,7 @@ const overlay_buffer *ALLOCATE_OVERLAY_BUFFER(color_space cs, uint16 width, uint
}
}
status_t RELEASE_OVERLAY_BUFFER(const overlay_buffer *ob)
/* Note that the user can delete the buffers in any order desired! */
{
src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c
+11 -12
View File
@@ -513,7 +513,7 @@ status_t nv_acc_init_dma()
ACCW(PR_CTX0_C, 0x00023002);
}
ACCW(PR_CTX1_C, 0x000fffff); /* DMA limit: tablesize is 1M bytes */
ACCW(PR_CTX2_C, (((uint32)((uint8 *)(si->dma_buffer_pci))) | 0x00000002));
ACCW(PR_CTX2_C, (((uintptr_t)((uint8 *)(si->dma_buffer_pci))) | 0x00000002));
/* DMA access type is READ_AND_WRITE;
* table is located in main system RAM (b12-31):
* It's adress needs to be at a 4kb boundary! */
@@ -1042,18 +1042,17 @@ status_t nv_acc_init_dma()
* b0-1 aren't used as adressbits. Using b0 to indicate a valid pointer. */
for (cnt = 0; cnt < 0x08; cnt++)
{
si->engine.fifo.ch_ptr[(si->engine.fifo.handle[cnt])] =
(0x00000001 + (cnt * 0x00002000));
si->engine.fifo.ch_ptr[(si->engine.fifo.handle[cnt])]
= (0x00000001 + (cnt * 0x00002000));
}
/*** init DMA command buffer info ***/
if (si->ps.card_arch >= NV40A) //main mem DMA buf on pre-NV40
{
si->dma_buffer = (void *)((char *)si->framebuffer +
((si->ps.memory_size - 1) & 0xffff8000));
si->dma_buffer = (void *)((char *)si->framebuffer
+ ((si->ps.memory_size - 1) & 0xffff8000));
}
LOG(4,("ACC_DMA: command buffer is at adress $%08x\n",
((uint32)(si->dma_buffer))));
LOG(4, ("ACC_DMA: command buffer is at adress $%p\n", si->dma_buffer));
/* we have issued no DMA cmd's to the engine yet */
si->engine.dma.put = 0;
/* the current first free adress in the DMA buffer is at offset 0 */
@@ -1076,9 +1075,7 @@ status_t nv_acc_init_dma()
if (si->ps.card_arch >= NV40A)
{
if (nv_acc_fifofree_dma(12) != B_OK) return B_ERROR;
}
else
{
} else {
if (nv_acc_fifofree_dma(16) != B_OK) return B_ERROR;
}
@@ -1888,9 +1885,10 @@ void SCREEN_TO_SCREEN_SCALED_FILTERED_BLIT_DMA(engine_token *et, scaled_blit_par
si->engine.threeD.reload = 0xffffffff;
}
/* scaled and filtered screen to screen blit - i.e. video playback without overlay */
/* note: source and destination may not overlap. */
//fixme? checkout NV5 and NV10 version of cmd: faster?? (or is 0x77 a 'autoselect' version?)
// FIXME? checkout NV5 and NV10 version of cmd: faster?? (or is 0x77 a 'autoselect' version?)
void OFFSCREEN_TO_SCREEN_SCALED_FILTERED_BLIT_DMA(
engine_token *et, offscreen_buffer_config *config, clipped_scaled_blit_params *list, uint32 count)
{
@@ -1898,7 +1896,8 @@ void OFFSCREEN_TO_SCREEN_SCALED_FILTERED_BLIT_DMA(
uint32 cmd_depth;
uint8 bpp;
LOG(4,("ACC_DMA: offscreen src buffer location $%08x\n", (uint32)((uint8*)(config->buffer))));
LOG(4, ("ACC_DMA: offscreen src buffer location $%p\n",
(uint8*)(config->buffer)));
/*** init acc engine for scaled filtered blit function ***/
/* Set pixel width */
src/add-ons/accelerants/nvidia/engine/nv_agp.c
+1 -1
View File
@@ -17,7 +17,7 @@ nv_agp_setup(bool enable_agp)
nv_nth_agp_info nai;
nv_cmd_agp nca;
uint8 index;
agp_info nv_ai;
agp_info nv_ai = {0};
bool agp = false;
/* preset we are running in PCI mode: so acc engine may not use AGP transfers */
src/add-ons/accelerants/nvidia/engine/nv_bes.c
+3 -3
View File
@@ -13,7 +13,7 @@ struct move_overlay_info
uint32 vcoordv; /* top and bottom edges of video output window */
uint32 hsrcstv; /* horizontal source start in source buffer (clipping) */
uint32 v1srcstv; /* vertical source start in source buffer (clipping) */
uint32 a1orgv; /* alternate source clipping via startadress of source buffer */
uintptr_t a1orgv; /* alternate source clipping via startadress of source buffer */
};
static void nv_bes_calc_move_overlay(move_overlay_info *moi);
@@ -235,8 +235,8 @@ static void nv_bes_calc_move_overlay(move_overlay_info *moi)
*******************************/
/* calculate inputbitmap origin adress */
moi->a1orgv = (uint32)((vuint32 *)si->overlay.ob.buffer);
moi->a1orgv -= (uint32)((vuint32 *)si->framebuffer);
moi->a1orgv = (uintptr_t)((vuint32 *)si->overlay.ob.buffer);
moi->a1orgv -= (uintptr_t)((vuint32 *)si->framebuffer);
LOG(4, ("Overlay: topleft corner of input bitmap (cardRAM offset) $%08x\n", moi->a1orgv));
/* Setup vertical source start: first (sub)pixel contributing to output picture. */
src/add-ons/accelerants/nvidia/engine/nv_dac.c
+10 -6
View File
@@ -312,6 +312,7 @@ static void nv_dac_dump_pix_pll(void)
DACW(PLLSEL, 0x10000700);
}
/* find nearest valid pix pll */
status_t nv_dac_pix_pll_find
(display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test)
@@ -322,13 +323,15 @@ status_t nv_dac_pix_pll_find
return B_ERROR;
}
/* find nearest valid pixel PLL setting */
static status_t nv4_nv10_nv20_dac_pix_pll_find(
display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test)
display_mode target, float* calc_pclk, uint8* m_result, uint8* n_result,
uint8* p_result, uint8 test)
{
int m = 0, n = 0, p = 0/*, m_max*/;
float error, error_best = 999999999;
int best[3];
float error, error_best = INFINITY;
int best[3] = {0, 0, 0};
float f_vco, max_pclk;
float req_pclk = target.timing.pixel_clock/1000.0;
@@ -473,11 +476,12 @@ static status_t nv4_nv10_nv20_dac_pix_pll_find(
/* find nearest valid system PLL setting */
status_t nv_dac_sys_pll_find(
float req_sclk, float* calc_sclk, uint8* m_result, uint8* n_result, uint8* p_result, uint8 test)
float req_sclk, float* calc_sclk, uint8* m_result, uint8* n_result,
uint8* p_result, uint8 test)
{
int m = 0, n = 0, p = 0, m_max, p_max;
float error, error_best = 999999999;
int best[3];
float error, error_best = INFINITY;
int best[3] = {0, 0, 0};
float f_vco, discr_low, discr_high;
/* determine the max. reference-frequency postscaler setting for the
src/add-ons/accelerants/nvidia/engine/nv_dac2.c
+5 -3
View File
@@ -280,13 +280,15 @@ status_t nv_dac2_pix_pll_find
return B_ERROR;
}
/* find nearest valid pixel PLL setting */
static status_t nv10_nv20_dac2_pix_pll_find(
display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test)
display_mode target, float* calc_pclk, uint8* m_result, uint8* n_result,
uint8* p_result, uint8 test)
{
int m = 0, n = 0, p = 0/*, m_max*/;
float error, error_best = 999999999;
int best[3];
float error, error_best = INFINITY;
int best[3] = {0, 0, 0};
float f_vco, max_pclk;
float req_pclk = target.timing.pixel_clock/1000.0;
src/add-ons/accelerants/nvidia/engine/nv_info.c
+22 -10
View File
@@ -133,6 +133,7 @@ status_t parse_pins ()
return B_OK;
}
static status_t pins2_read(uint8 *rom, uint32 offset)
{
uint16 init1 = rom[offset + 18] + (rom[offset + 19] * 256);
@@ -141,12 +142,17 @@ static status_t pins2_read(uint8 *rom, uint32 offset)
/* confirmed by comparing cards */
uint16 ram_tab = init1 - 0x0010;
/* fixme: PPC BIOSes (might) return NULL pointers for messages here */
char* signon_msg = &(rom[(rom[offset + 24] + (rom[offset + 25] * 256))]);
char* vendor_name = &(rom[(rom[offset + 40] + (rom[offset + 41] * 256))]);
char* product_name = &(rom[(rom[offset + 42] + (rom[offset + 43] * 256))]);
char* product_rev = &(rom[(rom[offset + 44] + (rom[offset + 45] * 256))]);
unsigned char* signon_msg
= &(rom[(rom[offset + 24] + (rom[offset + 25] * 256))]);
unsigned char* vendor_name
= &(rom[(rom[offset + 40] + (rom[offset + 41] * 256))]);
unsigned char* product_name
= &(rom[(rom[offset + 42] + (rom[offset + 43] * 256))]);
unsigned char* product_rev
= &(rom[(rom[offset + 44] + (rom[offset + 45] * 256))]);
LOG(8,("INFO: cmdlist 1: $%04x, 2: $%04x, max. size $%04x\n", init1, init2, init_size));
LOG(8, ("INFO: cmdlist 1: $%04x, 2: $%04x, max. size $%04x\n", init1, init2,
init_size));
LOG(8, ("INFO: signon msg:\n%s\n", signon_msg));
LOG(8, ("INFO: vendor name: %s\n", vendor_name));
LOG(8, ("INFO: product name: %s\n", product_name));
@@ -155,6 +161,7 @@ static status_t pins2_read(uint8 *rom, uint32 offset)
return coldstart_card(rom, init1, init2, init_size, ram_tab);
}
static status_t pins3_5_read(uint8 *rom, uint32 offset)
{
uint16 init1 = rom[offset + 18] + (rom[offset + 19] * 256);
@@ -163,12 +170,17 @@ static status_t pins3_5_read(uint8 *rom, uint32 offset)
/* confirmed on a TNT2-M64 with pins V5.1 */
uint16 ram_tab = rom[offset + 24] + (rom[offset + 25] * 256);
/* fixme: PPC BIOSes (might) return NULL pointers for messages here */
char* signon_msg = &(rom[(rom[offset + 30] + (rom[offset + 31] * 256))]);
char* vendor_name = &(rom[(rom[offset + 46] + (rom[offset + 47] * 256))]);
char* product_name = &(rom[(rom[offset + 48] + (rom[offset + 49] * 256))]);
char* product_rev = &(rom[(rom[offset + 50] + (rom[offset + 51] * 256))]);
unsigned char* signon_msg
= &(rom[(rom[offset + 30] + (rom[offset + 31] * 256))]);
unsigned char* vendor_name
= &(rom[(rom[offset + 46] + (rom[offset + 47] * 256))]);
unsigned char* product_name
= &(rom[(rom[offset + 48] + (rom[offset + 49] * 256))]);
unsigned char* product_rev
= &(rom[(rom[offset + 50] + (rom[offset + 51] * 256))]);
LOG(8,("INFO: pre PINS 5.16 cmdlist 1: $%04x, 2: $%04x, max. size $%04x\n", init1, init2, init_size));
LOG(8, ("INFO: pre PINS 5.16 cmdlist 1: $%04x, 2: $%04x, max. size $%04x\n",
init1, init2, init_size));
LOG(8, ("INFO: signon msg:\n%s\n", signon_msg));
LOG(8, ("INFO: vendor name: %s\n", vendor_name));
LOG(8, ("INFO: product name: %s\n", product_name));